Altera Nios Development Board User Manual
Page 21
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Altera Corporation
2–13
July 2005
Nios Development Board Reference Manual, Stratix II Edition
Board Components
f
Refer to www.micron.com for detailed information.
DQ13
82
AF20
DQ14
83
AC17
DQ15
85
V17
DQ16
31
AB18
DQ17
33
AF21
DQ18
34
AD20
DQ19
36
AD21
DQ20
37
AF22
DQ21
39
AC18
DQ22
40
W18
DQ23
42
AB19
DQ24
45
AD22
DQ25
47
AE22
DQ26
48
AF24
DQ27
50
AE24
DQ28
51
AB7
DQ29
53
V10
DQ30
54
AA8
DQ31
56
AF3
DQM0
16
AF7
DQM1
71
AD7
DQM2
28
AC7
DQM3
59
AF8
RAS_N
19
AE17
CAS_N
18
AE16
CKE
67
AE20
CS_N
20
AE19
WE_N
17
AE18
CLK
68
AF12
Table 2–5. SDRAM (U57) Pin Table (Part 2 of 2)
Pin Name
Pin Number
Connects to Stratix II Pin
See also other documents in the category Altera Measuring instruments:
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)