Development board block diagram, Development board block diagram –3 – Altera Cyclone IV GX FPGA Development Board User Manual
Page 7

Chapter 1: Overview
1–3
Development Board Block Diagram
May 2013
Altera Corporation
Cyclone IV GX FPGA Development Board
Reference Manual
■
Power supply
■
16-V DC input
■
2.5-mm barrel jack for DC power input
■
On/Off slide power switch
■
On-Board power measurement circuitry
■
20-W per HSMC interface
■
Mechanical
■
PCIe small form factor board
■
Bench-top operation
Development Board Block Diagram
shows the block diagram of the Cyclone IV GX FPGA development board.
Figure 1–1. Cyclone IV GX FPGA Development Board Block Diagram
EP4CGX150DF31
XCVR x4
10/100/1000
Ethernet RGMII
Translator
User LEDs
Push-Button,
Switches
14-pin LCD
Header
CPLD
(x18)
64 MB Flash
(x16)
4 MB SSRAM
(x18)
RJ45
Jack
Power
Measure
1.8 V
CMOS
1.8 V
CMOS
LVDS
1.8 V
2.5 V
Port B
USB
Blaster
100 MHz XTAL
SMA Input
125 MHz XTAL
32 MB DDR2
(x32)
SMA Output
1.8 V
HSTL
32 MB DDR2
(x32)
Translator
Port A
Translator
For TX/RX
[8:16]
1.8 V
XCVR x4
2.5 V
1.8 V
2.5 V
1.8 V
x4 Edge
XCVR x4
2.5 V (For TX/RX [0:7])
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)