Altera Cyclone IV GX FPGA Development Board User Manual
Page 6

1–2
Chapter 1: Overview
Board Component Blocks
Cyclone IV GX FPGA Development Board
May 2013
Altera Corporation
Reference Manual
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On-Board memory
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4-MB (x16) Synchronous Static Random Access Memory (SSRAM)
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Two 32-MB (x32) DDR2 SDRAM
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64-MB flash
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On-Board clocking circuitry
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50.000-MHz oscillator
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125.000-MHz oscillator
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SMA clock input
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SMA clock output
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Programmable oscillator (default: 100.000-MHz)
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General user I/O
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LEDs and display
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Eight FPGA user LEDs
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One configuration done LED
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One error LED
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Five Ethernet status LEDs
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One USB status LED
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One power status LED
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Five configuration LEDs
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A two-line 16-character LCD display
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Push buttons
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One CPU reset push button
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One MAX II configuration reset push button
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One program-load push button—configure the FPGA from flash memory
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One program-select push button—select image to load from flash memory
or serial configuration (EPCS) device
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Four general user push buttons
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DIP switches
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Board settings DIP switch
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JTAG chain select DIP switch
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PCIe control DIP switch
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Configuration settings DIP switch
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User DIP switch
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)