Altera Cyclone IV GX FPGA Development Board User Manual
Page 18

2–10
Chapter 2: Board Components
MAX II CPLD EPM2210 System Controller
Cyclone IV GX FPGA Development Board
May 2013
Altera Corporation
Reference Manual
FSM_A1
1.8-V
P7
AD6
FSM bus address
FSM_A2
R6
AK29
FSM bus address
FSM_A3
R5
AA21
FSM bus address
FSM_A4
R4
AG25
FSM bus address
FSM_A5
R3
AH5
FSM bus address
FSM_A6
M8
AH27
FSM bus address
FSM_A7
P6
AJ12
FSM bus address
FSM_A8
P8
AF16
FSM bus address
FSM_A9
R7
AH20
FSM bus address
FSM_A10
N6
AK23
FSM bus address
FSM_A11
P4
AH17
FSM bus address
FSM_A12
P5
AB21
FSM bus address
FSM_A13
N8
AF19
FSM bus address
FSM_A14
T6
AF12
FSM bus address
FSM_A15
N5
AG27
FSM bus address
FSM_A16
M6
AK26
FSM bus address
FSM_A17
N7
AH4
FSM bus address
FSM_A18
T5
AK3
FSM bus address
FSM_A19
R1
AH9
FSM bus address
FSM_A20
M7
AG6
FSM bus address
FSM_A21
T2
AK25
FSM bus address
FSM_A22
T7
AE21
FSM bus address
FSM_A23
T4
AA18
FSM bus address
Table 2–5. MAX II CPLD EPM2210 System Controller Device Pin-Out (Part 3 of 4)
Schematic Signal Name
I/O
Standard
EPM2210
Pin Number
EP4CGX15BF14
Pin Number
Description
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)