Development board block diagram, Development board block diagram –4 – Altera Transceiver Signal Integrity Development Kit, Stratix IV GT Edition User Manual
Page 8
1–4
Chapter 1: Overview
Development Board Block Diagram
Transceiver Signal Integrity Development Kit,
November 2011
Altera Corporation
Stratix IV GT Edition Reference Manual
Development Board Block Diagram
shows the block diagram of the Stratix IV GT transceiver signal integrity
board.
Figure 1–1. Stratix IV GT Transceiver Signal Integrity Board Block Diagram
GT
LCD
Power
Measure
24-bit
ADC
Dual Temp
Sensor
Temp
Measure
TDIODES
5-V FAN
USB-Blaster
USB
Type-B
Conn
USB
PHY
MAX
7064A
CPLD
10/100/1000
Ethernet
RJ45
Magnetics
SMSC
8700
Ethernet
PHY
FPP
Configuration
Clock
Circuitry
512-Mbit
Flash
Configuration
Status
LEDs
MAX
7256A
CPLD
PGMSEL
Jumper
2 Reset
Buttons
Buttons
Switches
Displays
Rotary
Switch
16 Char × 2 Line LCD
8 User DIP
6 User
Buttons
8 User
LEDs
Transceivers
Flash
FPP Config
2-wire Ch1
Power
Circuitry
2-wire Ch8
EP4S100G2F40I2N
Backplane
Connectors
ADC
Header
Pwrgood
TEMP
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)