Altera Transceiver Signal Integrity Development Kit, Stratix IV GT Edition - Manual (Page 25)

Chapter 2: Board Components 2–15
Clocks
November 2011 Altera Corporation Transceiver Signal Integrity Development Kit,
Stratix IV GT Edition Reference Manual
Table 2–10. Stratix IV GT Transceiver Signal Integrity Board Clock Distribution
Frequency Signal Name Signal Originates From
Signal
Propagates To
50 MHz
MAXII_50M_CLK
S4GT_50M_CLK4P
U20 pin 8
U20 pin 7
U32 pin H5
U33 pin AR22
User Input
S4GT_EXT_CLK5P
S4GT_EXT_CLK5N
SMA J14
SMA J15
U33 pin AV22
U33 pin AW22
User Defined IO_CLKOUT1 U33 pin M20 SMA J16
User Defined IO_CLKOUT2 U33 pin L20 SMA J17
25 MHz, 100 MHz, 125 MHz, 200 MHz
(Y2)
(Frequencies set by switch SW2)
S4GT_CLK1P
S4GT_CLK1N
U21 pin 15
U21 pin 14
U33 pin K34
U33 pin J34
User Input
EXT_REFCLK4P_GXB2
EXT_REFCLK4N_GXB2
SMA J19
SMA J20
U33 pin J38
U33 pin J39
644.53 MHz
(Y3)
644.53M_REFCLK2P_GXB1
644.53M_REFCLK2N_GXB1
U22 pin 20
U22 pin 19
U33 pin AA38
U33 pin AA39
706.25 MHz
(Y5)
706.25M_REFCLK3P_GXB1
706.25M_REFCLK3N_GXB1
U24 pin 1
U24 pin 2
U33 pin W38
U33 pin W39
100 MHz
(Y4)
100M_REFCLK5P_GXB2
100M_REFCLK5N_GXB2
U23 pin 1
U23 pin 2
U33 pin G38
U33 pin G39
25 MHz, 100 MHz, 125 MHz, 200 MHz X2 Trigger U21 pin 11 SMA J18
644.53 MHz
(Y3)
Y3 Trigger U22 pin 12 SMA J21
100 MHz
(Y4)
Y4 Trigger U23 pin 3 SMA J22
706.25 MHz
(Y5)
Y5 Trigger U24 pin 3 SMA J23