Altera Transceiver Signal Integrity Development Kit, Stratix IV GT Edition - Manual (Page 20)

2–10 Chapter 2: Board Components
Configuration, Status, and Setup Elements
Transceiver Signal Integrity Development Kit, November 2011 Altera Corporation
Stratix IV GT Edition Reference Manual
A green USB-Blaster LED (D7) is also provided to indicate USB-Blaster activity. The
embedded USB-Blaster is automatically disabled when an external USB-Blaster
connects to the JTAG chain at header J28.
Figure 2–3 shows the block diagram for the
embedded USB-Blaster.
Fast Passive Parallel Download
Figure 2–4 shows the block diagram for the MAX II+Flash FPP configuration. This
method is used for automatic configuration of the FPGA with the configuration
programming image stored in the flash memory. The FPP download controller is
implemented within an Altera EPM1270F256C3N MAX II CPLD (U32). This
controller, together with the Numonyx PC28F512P30BF 512-Mb CFI NOR-type flash
memory (U39), performs the FPP configuration upon board power-up or reset. The
CPLD shares the flash interface with the FPGA. The configuration program select
jumper, PGMSEL, (J62) selects between two Programmer Object Files (.pof)—factory
.pof
or user .pof file stored in the flash. The FPP controller uses the Altera Parallel
Flash Loader (PFL) megafunction to configure the FPGA by reading data from the
flash and converting it to FPP format. This data is written to the FPGA’s dedicated
configuration pins during configuration. The configuration mode select signals,
MSEL[2:0]
, are pulled to [0,0,0] on the board for FPP mode configuration. Three
green configuration status LEDs (D16–D18) indicate the status of the FPP
configuration.
Figure 2–3. Embedded USB-Blaster
USB Type-B
Connector
(CN1)
FTDI
FT245BL
USB PHY
(U16)
USB FIFO BUS
EPM7064
MAX II
CPLD
(U17)
JTAG
JT
A
G
JTAG Programming
Header (J28)
USB
Stratix IV GT
FPGA (U33)
Figure 2–4. MAX II+Flash FPP Configuration
RESET
Push-Button
(SW8)
PGMSEL
Jumper (J62)
MAX II CPLD
(U32)
FPP Configuration
Flash
Flash
Flash
(U39)
FA
CT
OR
Y LED
(D17)
USER LED
(D18)
ERR
OR LED
(D16)
Stratix IV GT
FPGA
(U33)