Altera Transceiver Signal Integrity Development Kit, Stratix IV GT Edition - Manual (Page 12)

2–2 Chapter 2: Board Components
Board Overview
Transceiver Signal Integrity Development Kit, November 2011 Altera Corporation
Stratix IV GT Edition Reference Manual
Board Overview
This section provides an overview of the Stratix IV GT transceiver signal integrity
development board, including an annotated board image and component
descriptions.
Figure 2–1 provides an overview of the board features.
Table 2–1 describes the components and lists their corresponding board references.
Figure 2–1. Overview of the Stratix IV GT Transceiver Signal Integrity Board Features
Power
Switch
(SW1)
DC Power Jack (J1)
Power LED
(D3)
LCD Display (J24)
Power
Circuit
(U1-U13)
MAX II CPLD (U32)
Flash Memory (U39)
Power Select Switch (SW16)
Spread Spectrum
Clock (X2, U21)
IO CLK OUT from
FPGA to SMA (J16, J17)
Config
Program
Selection
Jumper
(J62)
User DIP Switches (SW7)
706.25 MHz Osc (Y5)
External Clock
SMA to FPGA
(J14, J15)
100 MHz Osc (Y4)
644.53 MHz Osc (Y3)
CPU Reset (SW9)
Board Reset (SW8)
Config Status LEDs
(D16-D18)
Fan Connector (J12)
Fan Jumper (J64)
Fan LED (D6)
Embedded USB-Blaster Activity LED (D7)
GXB2
TX/RX
SMAs
(J30-J37)
GXB1
TX/RX
SMAs
(J38-J45,
J54-J61)
Ethernet Status
LEDs (D19-D24)
Embedded USB-Blaster (CN1)
Stratix IV GT FPGA (U33)
10/100 /1000 Ethernet (J68)
User Push-Buttons
(SW10-SW15)
User LEDs (D8-D15)
External Power
Input Banana Jacks
(J2-J4, J7-J10)
GXB0 TX/RX
to Backplane
Connector
(J70-J71)
External
Refclk
SMAs
(J19, J20)
Table 2–1. Stratix IV GT Transceiver Signal Integrity Development Board Components (Part 1 of 4)
Board Reference Type Description
Featured Devices
U33 EP4S100G2F40I1N Stratix IV GT device in a 1517-pin FBGA package.
Configuration, Status, and Setup Elements
J28 JTAG programming header
JTAG programming header for connecting an Altera USB-Blaster
dongle to program the FPGA and MAX II CPLD devices.
J26
MAX II JTAG configuration
jumper Jumper to bypass the MAX II CPLD from the JTAG programming
chain.
J63
JTAG for embedded
USB-Blaster MAX II CPLD
JTAG for embedded USB-Blaster MAX II CPLD device programming.