Altera Active Serial Memory Interface - Manual (Page 29)

EPCQ/EPCQ-L device, and discards the first few bytes. This behavior is consistent
with the EPCS/EPCQ/EPCQ-L device itself.
Note: The
shift_bytes
, wren, and
datain[7..0]
ports must adhere to setup and hold
time requirements for the
clkin
signal. These ports must remain stable at the
rising edge of the
clkin
signal.
For stage 2, you must ensure that the start memory address to be written appears on the
addr[23..0]
signal before you assert the
write
signal. When you have completed sending all
data bytes, assert the
write
signal to indicate to the IP core that the internal write can proceed.
The IP core registers both the
write
and
addr[23..0]
ports on the rising edge of the
clkin
signal. You need to only send the start memory address to be written to. The EPCS/EPCQ/EPCQ-
L device treats the address increment internally.
Caution: If the eight least significant address bits of the
addr[7..0]
are not all zero, the
IP core does not write sent data that continues beyond the end of the current
page into the next page. Instead, this data is written at the start memory
address of the same page (from the address whose eight least significant
address bits are all
0
).
The IP core passes the data that you supply and the memory address as it is to the EPCS/EPCQ/
EPCQ-L device. To avoid unexpected rearrangement of data order by the EPCS/EPCQ/EPCQ-L
write operation, use a
PAGE_SIZE
of 256 bytes, and execute page-write operations at the start of
each page boundary (where the
addr[7..0]
bits are all
0
).
The IP core asserts the
busy
signal after receiving the write command.
The
busy
signal remains asserted while the EPCS/EPCQ/EPCQ-L device is writing into the
memory.
If the
wren
signal has a value of zero, the IP core will not carry out the write operation, and the
busy
signal remains deasserted.
If the memory region is protected (you can set this in the EPCS/EPCQ/EPCQ-L status register),
the write operation does not proceed, and the
busy
signal is deasserted. The IP core then asserts
the
illegal_write
signal for two clock cycles to indicate that the write operation has been
cancelled.
If you keep both the
wren
and
write
signals asserted while the
busy
signal is deasserted after the
IP core has finished processing the write command, the IP core re-registers the
wren
and
write
signals as a value of one, and carries out another write command. Therefore, before the IP core
deasserts the
busy
signal, you must deassert the
wren
and
write
signals.
Note: For EPCQ256/EPCQ_L256 or larger devices, the width of the
addr
and
read_address
signals is 32 bit.
Note: Use the SCFIFO IP core as the storage buffer for the page write operation. This
allows you to select the RAM or LEs as the storage buffer.
Read Status Register of the EPCS/EPCQ/EPCQ-L Device
Use the
read_status
signal to instruct the IP core to read the status register of the EPCS/EPCQ/EPCQ-L
device.
UG-ALT1005
2014.12.15
Read Status Register of the EPCS/EPCQ/EPCQ-L Device 29
Altera ASMI Parallel IP Core User Guide Altera Corporation
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