Altera Active Serial Memory Interface - Manual (Page 23)

The first data byte then appears on the
dataout[7..0]
signal. The IP core then asserts the
data_valid
signal for one clock cycle, which indicates that the
dataout[7..0]
signal contains a
new valid data.
If you enable the
read_address[23..0]
port in the IP parameter editor, the port reflects the
memory address for each data byte that appears on
dataout[7..0]
signal.
If you want to continue reading sequential data from the EPCS/EPCQ/EPCQ-L device, the
rden
signal must remain asserted. This condition allows you to read every memory address from the
EPCS/EPCQ/EPCQ-L device with a single read command.
For every eight
clkin
signal clock cycles, a new data byte from the next address appears on the
dataout[7..0]
signal with its corresponding memory address on the
read_address[23..0]
signal. The
data_valid
signal is asserted for one clock cycle after the new data byte is out on the
dataout[7..0]
signal. Use the
data_valid
signal as an indication to capture the new data byte.
After the second-to-last byte of data to be read appears on the
dataout[7..0]
signal, and the
data_valid
signal is asserted, deassert the
rden
signal to indicate the end of the read command.
A new byte from the next address then appears on the
dataout[7..0]
signal, and the
data_valid
signal is reasserted before the IP core stops processing. Only then does the IP core
deassert the
busy
signal.
For a single-byte read, simply assert the rden signal for one clock cycle in conjunction with the
read signal, or deassert the
rden
signal any time before the first data appears on the
dataout[7..0]
signal, and the
data_valid
signal asserts for the first time.
Monitor the
data_valid
signal and sample the
dataout[7..0]
signal only when the
data_valid
signal has a value of one.
After read operation, the
dataout[7..0]
signal holds the value of the last byte read until you
issue a new read command or reset the device.
Note: The
read
,
rden
, and
addr[7..0]
signals must adhere to setup and hold time
requirements for the
clkin
signal. These signals must remain stable at the rising
edge of the
clkin
signal.
Note: For EPCQ256/EPCQ_L256 or larger devices, the width of the
addr
and
read_address
signals is 32 bit.
Fast Read Data from the EPCS/EPCQ/EPCQ-L Device
Use the
fast_read
signal to instruct the IP core to read data from the EPCS/EPCQ/EPCQ-L device. The
Altera ASMI Parallel IP core supports two types of fast read data operation: multiple-byte and single-byte
operation.
UG-ALT1005
2014.12.15
Fast Read Data from the EPCS/EPCQ/EPCQ-L Device 23
Altera ASMI Parallel IP Core User Guide Altera Corporation
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