Device family support, Series – Altera Active Serial Memory Interface User Manual
Page 2
This figure shows that you can use the Altera ASMI Parallel IP core to access the general purpose memory
portion of the EPCS/EPCQ/EPCQ-L devices through the supported Altera devices.
Caution:
Altera recommends you to be cautious when accessing the configuration memory in the EPCS/
EPCQ/EPCQ-L device to avoid corrupting the configuration bits.
Example 1: Accessing General Purpose Memory in Altera Devices
Altera Device
ASMI Controller
read_block
write_block
erase_bulk_block/erase_die_block
read_silicon_id_block
(3)
write_status_block
Clock
Divider
ASDI
nCS
DCLK
DATA
EPCS Device
User Design
stratixii_asmiblock,
stratixiigx_asmiblock,
stratixiii_asmiblock,
stratixv_asmiblock
arriagx_asmiblock
arriavgz_asmiblock,
stratixiv_asmiblock,
arriav_asmiblock,
arriaiigz_asmiblock,
arriaii_asmiblock,
cycloneii_asmiblock ,
(2)
cyclone_asmiblock,
cyclonev_asmiblock,
ASMI Device Primitives
Altera ASMI PARALLEL IP Core
read_memory_capacity_id
(1)
fast_read
(1)
nCS
DCLK
DATA0
DATA1
DATA2
DATA3
EPCQ/EPCQ-L
Device
(1) Not applicable for EPCS1 and EPCS4.
(2) The synthesis operations for Cyclone III, Cyclone IV GX, and Cyclone IV E devices use the cycloneii_asmi primitive.
(3) The read_silicon_id block is supported only for EPCS1, EPCS4, EPCS16 and EPCS64.
erase_sector_block
twentynm_asmiblock
(5)
(4)
(4) Only available for Arria 10 devices.
(5) The erase_die_bloack is only available for EPCQ-L512 and EPCQ-L1024 device.
Related Information
•
Introduction to Altera IP Cores
For more information about Altera IP cores
•
For more information about AS configuration
•
For more information about EPCS devices
•
•
•
For more information about features, memory array organization, and operation codes of the EPCS
device
Device Family Support
The Altera ASMI Parallel IP core is available for all Altera device families supported by the Quartus II
software except the MAX
®
series.
2
Device Family Support
UG-ALT1005
2014.12.15
Altera Corporation
Altera ASMI Parallel IP Core User Guide