Spectrum Controls 1746sc-NI8u - Manual (Page 8)

iv SLC 500 ™ Universal Analog Input Modules
Local System - A control system with I/O chassis within several feet of
the processor, and using 1746-C7 or 1746-C9 ribbon cable for
communication.
LSB (least significant bit) – The bit that represents the smallest value
within a string of bits. The “weight” of this value is defined as the full-
scale range divided by the resolution.
Mulitplexer – A switching system that allows several input signals to
share a common A/D converter.
Normal mode rejection (differential mode rejection) – A logarithmic
measure, in dB, of a device’s ability to reject noise signals between or
among circuit signal conductors, but not between the equipment grounding
conductor or signal reference structure and the signal conductors.
Module update time – See channel update time.
Remote system - A control system shere the chassis can be located
several thousand feet from the processor chassis. Chassis communication
is via the 1747-SN Scanner and 1747-ASB Remote I/O Adapter.
Resolution – The smallest detectable change in a measurement, typically
expressed in engineering units (e.g. 0.15 °C) or as a number of bits. For
example, a 12-bit system has 4096 possible output states. It can therefore
measure 1 part in 4096. See also effective resolution.
RTD (Resistance Temperature Detector) - A temperature sensing
element with 2, 3, 4, lead wires. It uses the basic characteristics that
electrical resistance of metals increases with temperature. When a small
current is applied to the RTD, it creates a voltage that varies with
temperature. This voltage is processed and converted by the RTD module
into a temperature value.
Sampling time - The time required by the A/D converter to sample an
input channel.
Status word – Contains status information about the channel’s current
configuration and operational state. You can use this information in your
ladder program to determine whether the channel data word is valid.
Step response time – The time required for the A/D signal to reach
95% of its expected, final value, given a full-scale step change in the
output data word.
Update time – The time for the module to sample and convert a channel
input signal and make the resulting value available to the SLC processor.