ADLINK ETX-PVR - Manual (Page 32)

Chapter 3 Hardware
26 Reference Manual ETX-PVR
55 PERR* Parity Error – This signal is driven by the PCI target during a write to indicate a
data parity error has been detected.
56 NC Not connected (Reserved)
57 PME* Power Management Event – This signal is an optional signal that can be used by
a device to request a change in the device or system power state.
58 USB2- Universal Serial Bus Port 2 Data Negative Polarity
59 LOCK* Lock – This signal indicates an operation that may require multiple transactions
to complete.
60 DEVSEL* Device Select – Driven by the target device when its address is decoded.
61 TRDY* Target Ready – This signal indicates the selected device’s ability to complete the
current cycle of transaction. Both IRDY and TRDY must be asserted to
terminate a data cycle.
62 USB3- Universal Serial Bus Port 3 Data Negative Polarity
63 IRDY* Initiator Ready – Indicates the master’s ability to complete the current data cycle.
64 STOP* Stop – Driven by the current PCI target when requesting the master stop the
current transaction.
65 FRAME* PCI bus Frame access – Driven by the current master to indicate the start of a
transaction and will remain active until the final data cycle.
66 USB2+ Universal Serial Bus Port 2 Data Positive Polarity
67,
68 GND Ground
69 AD16 Address/Data bus 16 – Refer to J1, pin-23 for more information.
70 CBE2* Bus Command and Byte Enable 2 – Refer to J1, pin-31 for more information.
71 AD17 Address/Data bus 17 – Refer to J1, pin-23 for more information.
72 USB3+ Universal Serial Bus Port 3 Data Positive Polarity
73 AD19 Address/Data bus 19 – Refer to J1, pin-23 for more information.
74 AD18 Address/Data bus 18 – Refer to J1, pin-23 for more information.
75 AD20 Address/Data bus 20 – Refer to J1, pin-23 for more information.
76 USB0- Universal Serial Bus Port 0 Data Negative Polarity
77 AD22 Address/Data bus 22 – Refer to J1, pin-23 for more information.
78 AD21 Address/Data bus 21 – Refer to J1, pin-23 for more information.
79 AD23 Address/Data bus 23 – Refer to J1, pin-23 for more information.
80 USB1- Universal Serial Bus Port 0 Data Negative Polarity
81 AD24 Address/Data bus 24 – Refer to J1, pin-23 for more information.
82 CBE3* Bus Command and Byte Enable 3 – Refer to J1, pin-31 for more information.
83,
84 VCC DC Power – +5 volts +/- 5%
85 AD25 Address/Data bus 25 – Refer to J1, pin-23 for more information.
86 AD26 Address/Data bus 26 – Refer to J1, pin-23 for more information.
87 AD28 Address/Data bus 28 – Refer to J1, pin-23 for more information.
88 USB0+ Universal Serial Bus Port 0 Data Positive Polarity
89 AD27 Address/Data bus 27 – Refer to J1, pin-23 for more information.
90 AD29 Address/Data bus 29 – Refer to J1, pin-23 for more information.
Table 3-4. Complete X1 Interface Pin Signal Descriptions (J1) (Continued)