Digilent DIO2 - Manual (Page 18)

Digilab DIO2 Reference Manual Digilent, Inc.
www.digilentinc.com page 18 of 19
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Configuration for DIO2 XC95108 CPLD
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity d2io is
Port ( btns : in std_logic_vector(14 downto 0);
switchs : in std_logic_vector(7 downto 0);
leds : out std_logic_vector(15 downto 0);
data : inout std_logic_vector(7 downto 0);
addr : in std_logic_vector(5 downto 0);
sseg : out std_logic_vector(6 downto 0);
ssegdp : out std_logic;
ssegsel : out std_logic_vector(3 downto 0);
cs, we, oe, clk256 : in std_logic);
end d2io;
architecture rtl of d2io is
signal data_out : std_logic_vector(7 downto 0);
signal sseg_reg, leds_i : std_logic_vector(15 downto 0);
signal sseg1 : std_logic_vector(6 downto 0);
signal digit : std_logic_vector(3 downto 0);
signal count : unsigned(1 downto 0);
signal testentry, testmode : std_logic;
signal ssegsel1 : std_logic_vector(3 downto 0);
begin
--
-- Button and switch reads (non-registered)
--
data <= data_out when (oe = '1' and cs = '1') else (others => 'Z');
data_out <= btns(7 downto 0) when addr(1 downto 0) = "00" else
'0'&btns(14 downto 8) when addr(1 downto 0) = "01" else switchs;
--
-- LED and SSD register writes
--
process(we)
begin
if(falling_edge(we) and cs = '1') then
case addr is
when "000100" => leds_i(7 downto 0) <= data;
when "000101" => leds_i(15 downto 8) <= data;
when "000110" => sseg_reg(15 downto 8) <= data;
when "000111" => sseg_reg(7 downto 0) <= data;
when others => NULL;
end case;
end if;
end process;
--
-- Seven segment controller
--
-- Generates anode and cathode signals from an input clock
-- and two 8-bit registers containing four 4-bit digit fields.