Kontron KT690-mITX (BGA) - dual core - Manual (Page 40)

KT690 Family
KTD-00738-J Public User Manual Date 2012-06-01 Page 40
Parallel ATA harddisk interface 4.6
One parallel ATA harddisk controllers is available on the board – a primary controller. Standard 3½”
harddisks or CD-ROM drives may be attached to the primary controller by means of the 40 pin IDC
connector, PATA.
The parallel ATA harddisk controller is shared between the PATA connector and the CF connector.
If the CF connector is not used then two devices (a primary and a secondary device) are supported on the
PATA interface.
The harddisk controllers support Bus master IDE, ultra DMA 33/66/100/133 MHz and standard operation
modes. For support of ultra DMA 66/100/133 MHz, a 80-wire cable is required.
If the CF connector is used then only one PATA device is supported and only by use of 40-wire cable (not
80-wire cable). Optionally use SATA device(s).
The signals used for the harddisk interface are the following:
Signal Description
DAA2..0 Address lines, used to address the I/O registers in the IDE hard disk.
HDCSA1..0# Hard Disk Chip-Select. HDCS0# selects the primary hard disk.
DA15..8 High part of data bus.
DA7..0 Low part of data bus.
IORA# I/O Read.
IOWA# I/O Write.
IORDYA# This signal may be driven by the hard disk to extend the current I/O cycle.
RESETA# Reset signal to the hard disk.
HDIRQA Interrupt line from hard disk.
CBLIDA This input signal (CaBLe ID) is used to detect the type of attached cable: 80-wire cable
when low input and 40-wire cable when 5V via 10Kohm (pull-up resistor).
DDREQA Disk DMA Request might be driven by the IDE hard disk to request bus master access to
the PCI bus. The signal is used in conjunction with the PCI bus master IDE function and is
not associated with any PC-AT bus compatible DMA channel.
DDACKA# Disk DMA Acknowledge. Active low signal grants IDE bus master access to the PCI bus.
HDACTA# Signal from hard disk indicating hard disk activity. The signal level depends on the hard
disk type, normally active low. The signals from primary and secondary controller are
routed together through diodes and passed to the connector FEATURE.
All of the above signals are compliant to [4].
The pinout of the connectors are defined in the following sections.