Cirrus Logic EP7309 - Manual (Page 38)

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Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved) DS507F2
EP7309
High-Performance, Low-Power System on Chip
1) See EP7309 Users’ Manual for pin naming / functionality.
2) For each pad, the JTAG connection ordering is input,
output, then enable as applicable.
201 D6 nMWE O 358
202 B4 nMOE O 360
204 E6 nCS[0] O 362
205 A3 nCS[1] O 364
206 D5 nCS[2] O 366
207 B3 nCS[3] O 368
208 A2 nCS[4] O 370
Table 21. JTAG Boundary Scan Signal Ordering (Continued)
LQFP
Pin No.
PBGA
Ball
Signal Type Position