Cirrus Logic EP7309 - Manual (Page 20)

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Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved) DS507F2
EP7309
High-Performance, Low-Power System on Chip
SSI1 Interface
Parameter Symbol Min Max Unit
ADCCLK falling edge to nADCCSS deassert delay time t
Cd
9 10 ms
ADCIN data setup to ADCCLK rising edge time t
INs - 15 ns
ADCIN data hold from ADCCLK rising edge time t
INh
- 14 ns
ADCCLK falling edge to data valid delay time t
Ovd
 7
13 ns
ADCCLK falling edge to data invalid delay time t
Od
 2
3 ns
ADC
CLK
nADC
CSS
ADCIN
ADC
OUT
t
INs
t
INh
t
Cd
t
Od
t
Ovd
Figure 7. SSI1 Interface Timing Measurement