Cirrus Logic EP7309 - Manual (Page 25)

DS507F2

Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved) 25
EP7309
High-Performance, Low-Power System on Chip
208-Pin LQFP Pin Diagram
Note: 1. N/C should not be grounded but left as no connects.
2. Pin differences between the EP7212 and the EP7309 are bolded.
160
159
158
157
53
54
55
56
57
58
59
60
61
62
63
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
106 107 108 109 11
0
11
2
11
3
11
4
11
5
11
6
11
7
11
8
11
9
120 121
64
65
67
68
69
70
71
72
73
74
75
66
98
99
100
101
102
103
104
122 124 125 126 127 128 129 130 105 131 132 133 13
4
156 155 154 153 152 151 150 149 148 147 146 145 144 143 140 139 138 137 136 141 142 13
5
161
162
163
164
165
166
167
168
169
170
171
172
173
174
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
201
202
203
204
205
206
207
208
200
175
176
177
178
179
123 111
EP7309
208-Pin LQFP
(Top View)
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 51 50 52 1
n
EXTPWR
BA
T
O
K
nP
OR
VSSOSC
VDDOSC
MOSCIN
MOSCOUT
n
URESE
T
WAKEUP
A[6]
D[6]
A[5]
D[5]
VDDIO
VSSIO
A[4]
D[4]
A[3]
D[3]
nPWRFL
A[2]
D[2]
A[1]
A[0]
D[0]
VDDCORE
VSSIO
VDDIO
CL[2]
CL[1]
FRM
M
DD[2]
DD[1]
DD[0]
N/C
N/C
N/C
VDDIO
VSSIO
N/C
nMWE
nMOE
nCS[0]
nCS[1]
nCS[2]
nCS[3]
D[
7
]
A[
7]
D[
8
]
A[
8]
D[
9
]
D[
1
0
]
A[
10
]
VSSI
O
VD
DIO
A[
11
]
D[
1
2
]
A[
12
]
D[
1
3
]
A[
13
]
D[
1
4
]
DD[3]
D[
1
7
]
D[
1
5
]
A[
17
]
nTR
S
T
VSSI
O
VD
DIO
D[
1
8
]
A[
18
D[
1
9
]
A[
19
]
D[
2
0
]
VSSI
O
A[
21
]
D[
2
2
]
D[
2
3
]
A[
23
]
D[
2
4
]
VSSI
O
VD
DIO
A[
24
]
HA
LF
WO
RD
A[
14
]
n
BATCH
G
A[25]
D[25]
D[27]
A[27]
VSSIO
D[28]
D[29]
D[30]
D[31]
BUZ
COL[0]
COL[1]
TCLK
VDDIO
COL[2]
COL[3]
COL[4]
COL[5]
COL[6]
COL[7]
FB[0]
VSSIO
FB[1]
ADCOUT
ADCCLK
DRIVE[0]
VDDIO
PD[2]
VSSIO
VSSCORE
nADCCS
ADCIN
SSIRXDA
SSIRXFR
SSITXDA
SSITXFR
VSSIO
SSICLK
PD[0]/LEDFLSH
PD[1]
PD[3]
A[
22
]
PD[4]
VDDIO
PD[5]
PD[6]
DRIVE[1]
PD[7]
D[26]
A[
15
]
D[
1
6
]
A[
16
]
nCS[4]
VDDCORE
A[26]
D[
2
1
]
TMS
A[
20
]
SMPCLK
D[
1
1
]
A[
9]
D[1]
VSSCORE
N/C
N/C
VSSI
O
VSSIO
VSSIO
VSSIO
EXPC
LK
WO
RD
WRI
T
E
R
UN/
CLK
E
N
EXPRDY
PB[7
]
PB[6
]
PB[5
]
PB[4
]
PB[3
]
PB[2
]
PB
[1]
VSSI
O
TDI
VDDI
O
TD
O
PE[2
]/C
LKSE
L
nEXTFIQ
PA
[6
]
PA
[5
]
PA[4
]
PA
[3
]
PA
[2
]
PA
[1
]
PA
[0
]
LED
DRV
TXD[2] PH
DIN CT
S
RXD
[2
]
DC
D
DS
R
R
T
CO
UT
RT
CIN
VSSIO
PA
[7
]
VDD
IO
VSSI
O
nC
S
[5]
PB
[0]
TXD[1] RXD
[1]
nT
E
S
T
[1
]
nT
E
S
T
[0
]
EINT[3
]
nE
IN
T[
2
]
nE
IN
T[
1
]
PE[1
]BOO
T
SEL
[1
]
PE[0
]BOO
T
SEL
[0
]
N/C
VSSR
TC
VDDR
TC
Figure 12. 208-Pin LQFP (Low Profile Quad Flat Pack) Pin Diagram
nM
E
D
CH
G
/n
B
RO
M