Cirrus Logic AN366 - Manual (Page 21)

AN366
AN366REV2 21
RESTORE REGISTERS
Various configurations include writes to registers (see Figure 14):
Config 0 Register
SDI = 0x80
0x40 0x400000 Write Register Config0
SDO = 0xFF 0xFF 0xFFFFFF (Page 0, Register 0)
SDI = 0x80 0x00 0xFFFFFF Read Register Config0
SDO = 0xFF 0xFF 0x400000 (Page 0, Register 0)
Config 1 Register
SDI = 0x80
0x41 0x10FEE0 Write Register Config1
SDO = 0xFF 0xFF 0xFFFFFF (Page 0, Register 1)
SDI = 0x80 0x01 0xFFFFFF Read Register Config1
SDO = 0xFF 0xFF 0x10FEE0 (Page 0, Register 1)
Pulse Control Register
SDI = 0x80
0x49 0x000000 Write Register Pulse Control
SDO = 0xFF 0xFF 0xFFFFFF (Page 0, Register 9)
SDI = 0x80 0x09 0xFFFFFF Read Register Pulse Control
SDO = 0xFF 0xFF 0x000000 (Page 0, Register 9)
Phase Comp Register
SDI = 0x80
0x45 0x007C40 Write Register Phase Compensation
SDO = 0xFF 0xFF 0xFFFFFF (Page 0, Register 5)
SDI = 0x80 0x05 0xFFFFFF Read Register Phase Compensation
SDO = 0xFF 0xFF 0x007C40 (Page 0, Register 5)
Pulse Width Register
SDI = 0x80
0x48 0x0613F0 Write Register Pulse Width
SDO = 0xFF 0xFF 0xFFFFFF (Page 0, Register 8)
SDI = 0x80 0x08 0xFFFFFF Read Register Pulse Width
SDO = 0xFF 0xFF 0x0613F0 (Page 0, Register 8)
Pulse Rate Register
SDI = 0x92
0x5C 0x800000 Write Register Pulse Rate
SDO = 0xFF 0xFF 0xFFFFFF (Page 18, Register 28)
SDI = 0x92 0x1C 0xFFFFFF Read Register Pulse Rate
SDO = 0xFF 0xFF 0x800000 (Page 18, Register 28)
Sample Count Register
SDI = 0x90
0x73 0x000FA0 Write Register Sample Count
SDO = 0xFF 0xFF 0xFFFFFF (Page 16, Register 51)
SDI = 0x90 0x33 0xFFFFFF Read Register Sample Count
SDO = 0xFF 0xFF 0x000FA0 (Page 16, Register 51)
Settle Time
SDI = 0x90
0x79 0x800000 Write Register T Settle
SDO = 0xFF 0xFF 0xFFFFFF (Page 16, Register 57)
SDI = 0x90 0x39 0xFFFFFF Read Register T Settle
SDO = 0xFF 0xFF 0x800000 (Page 16, Register 57)
2 1
4 3
RESTORE
CONFIGURATIONS