Analog Devices ADuC812 - Manual (Page 53)

REV. B
ADuC812
–53–
Parameter Min Typ Max Unit Figure
SPI MASTER MODE TIMING (CPHA = 0)
t
SL
SCLOCK Low Pulsewidth 330 ns 58
t
SH
SCLOCK High Pulsewidth 330 ns 58
t
DAV
Data Output Valid after SCLOCK Edge 50 ns 58
t
DOSU
Data Output Setup before SCLOCK Edge 150 ns 58
t
DSU
Data Input Setup Time before SCLOCK Edge 100 ns 58
t
DHD
Data Input Hold Time after SCLOCK Edge 100 ns 58
t
DF
Data Output Fall Time 10 25 ns 58
t
DR
Data Output Rise Time 10 25 ns 58
t
SR
SCLOCK Rise Time 10 25 ns 58
t
SF
SCLOCK Fall Time 10 25 ns 58
t
DAV
MISO
MOSI
SCLOCK
(CPOL=1)
SCLOCK
(CPOL=0)
t
SH
t
SL
t
SR
t
SF
t
DOSU
t
DF
t
DR
t
DSU
t
DHD
MSB BIT 6 – 1 LSB
BIT 6 – 1 LSB IN MSB IN
Figure 57. SPI Master Mode Timing (CPHA = 0)