Analog Devices ADuC812 - Manual (Page 50)

REV. B
ADuC812
–50–
12 MHz Variable Clock
Parameter Min Typ Max Min Typ Max Unit Figure
UART TIMING (Shift Register Mode)
t
XLXL
Serial Port Clock Cycle Time 1.0 12t
CK
µs
55
t
QVXH
Output Data Setup to Clock 700 10t
CK
– 133 ns 55
t
DVXH
Input Data Setup to Clock 300 2t
CK
+ 133 ns 55
t
XHDX
Input Data Hold after Clock 0 0 ns 55
t
XHQX
Output Data Hold after Clock 50 2t
CK
– 117 ns 55
ALE (O)
TxD
(OUTPUT CLOCK)
RxD
(OUTPUT DATA)
RxD
(INPUT DATA)
t
XLXL
t
QVXH
t
XHQX
t
DVXH
t
XHDX
SET RI
OR
SET TI
0 6
MSB BIT6 BIT1
MSB BIT6 BIT1 LSB
7
LSB
1
Figure 54. UART Timing in Shift Register Mode