Aduc812 – Analog Devices ADuC812 User Manual
Page 5
REV. B
–5–
ADuC812
ADuC812BS
Parameter
V
DD
= 5 V
V
DD
= 3 V
Unit
Test Conditions/Comments
DIGITAL OUTPUTS
Output High Voltage (V
OH
)
2.4
V min
V
DD
= 4.5 V to 5.5 V
I
SOURCE
= 80
µA
4.0
2.6
V typ
V
DD
= 2.7 V to 3.3 V
I
SOURCE
= 20
µA
Output Low Voltage (V
OL
)
ALE,
PSEN, Ports 0 and 2
0.4
V max
I
SINK
= 1.6 mA
0.2
0.2
V typ
I
SINK
= 1.6 mA
Port 3
0.4
V max
I
SINK
= 8 mA
0.2
0.2
V typ
I
SINK
= 8 mA
Floating State Leakage Current
±10
µA max
±5
±5
µA typ
Floating State Output Capacitance
10
10
pF typ
POWER REQUIREMENTS
14, 15, 16
I
DD
Normal Mode
17
43
mA max
MCLKIN = 16 MHz
32
16
mA typ
MCLKIN = 16 MHz
26
12
mA typ
MCLKIN = 12 MHz
8
3
mA typ
MCLKIN = 1 MHz
I
DD
Idle Mode
25
mA max
MCLKIN = 16 MHz
18
17
mA typ
MCLKIN = 16 MHz
15
6
mA typ
MCLKIN = 12 MHz
7
2
mA typ
MCLKIN = 1 MHz
I
DD
Power-Down Mode
18
50
50
µA max
5
5
µA typ
NOTES
1
Specifications apply after calibration.
2
Temperature range –40
°C to +85°C.
3
Linearity is guaranteed during normal MicroConverter Core operation.
4
Linearity may degrade when programming or erasing the 640 Byte Flash/EE space during ADC conversion times due to on-chip charge pump activity.
5
Measured in production at V
DD
= 5 V after Software Calibration Routine at 25
°C only.
6
User may need to execute Software Calibration Routine to achieve these specifications, which are configuration dependent.
7
The offset and gain calibration spans are defined as the voltage range of user system offset and gain errors that the ADuC812 can compensate.
8
SNR calculation includes distortion and noise components.
9
Specification is not production tested, but is supported by characterization data at initial product release.
10
The temperature sensor will give a measure of the die temperature directly; air temperature can be inferred from this result.
11
DAC linearity is calculated using:
reduced code range of 48 to 4095, 0 to V
REF
range
reduced code range of 48 to 3995, 0 to V
DD
range
DAC output load = 10 k
Ω and 50 pF.
12
Flash/EE Memory Performance Specifications are qualified as per JEDEC Specification (Data Retention) and JEDEC Draft Specification A117 (Endurance).
13
Endurance Cycling is evaluated under the following conditions:
Mode
= Byte Programming, Page Erase Cycling
Cycle Pattern
= 00Hex to FFHex
Erase Time
= 20 ms
Program Time
= 100
µs
14
I
DD
at other MCLKIN frequencies is typically given by:
Normal Mode (V
DD
= 5 V):
I
DD
= (1.6 nAs
× MCLKIN) + 6 mA
Normal Mode (V
DD
= 3 V):
I
DD
= (0.8 nAs
× MCLKIN) + 3 mA
Idle Mode (V
DD
= 5 V):
I
DD
= (0.75 nAs
× MCLKIN) + 6 mA
Idle Mode (V
DD
= 3 V):
I
DD
= (0.25 nAs
× MCLKIN) + 3 mA
Where MCLKIN is the oscillator frequency in MHz and resultant I
DD
values are in mA.
15
I
DD
Currents are expressed as a summation of analog and digital power supply currents during normal MicroConverter operation.
16
I
DD
is not measured during Flash/EE program or erase cycles; I
DD
will typically increase by 10 mA during these cycles.
17
Analog I
DD
= 2 mA (typ) in normal operation (internal V
REF
, ADC and DAC peripherals powered on).
18
EA = Port0 = DV
DD
, XTAL1 (Input) tied to DV
DD
, during this measurement.
Typical specifications are not production tested, but are supported by characterization data at initial product release.
Specifications subject to change without notice.
Please refer to User Guide, Quick Reference Guide, Application Notes, and Silicon Errata Sheet at
for additional information.