Analog Devices ADuC812 - Manual (Page 31)

REV. B
ADuC812
–31–
1 F T 1 R T 0 F T 0 R T 1 E I
1
1 T I
1
0 E I
1
0 T I
1
NOTE
1 These bits are not used in the control of timer/counter 0 and 1, but are used instead in the control and monitoring of the external INT0 and INT1 interrupt pins.
Table XVII. TCON SFR Bit Designations
Bit Name Description
7 TF1 Timer 1 Overflow Flag.
Set by hardware on a timer/counter 1 overflow.
Cleared by hardware when the Program Counter (PC) vectors to the interrupt service routine.
6 TR1 Timer 1 Run Control Bit.
Set by user to turn on timer/counter 1.
Cleared by user to turn off timer/counter 1.
5 TF0 Timer 0 Overflow Flag.
Set by hardware on a timer/counter 0 overflow.
Cleared by hardware when the PC vectors to the interrupt service routine.
4 TR0 Timer 0 Run Control Bit.
Set by user to turn on timer/counter 0.
Cleared by user to turn off timer/counter 0.
3 IE1 External Interrupt 1 ( INT1) Flag.
Set by hardware by a falling edge or zero level being applied to external interrupt pin INT1,
depending on bit IT1 state.
Cleared by hardware when the when the PC vectors to the interrupt service routine only if the
interrupt was transition-activated. If level-activated, the external requesting source controls the
request flag, rather than the on-chip hardware.
2 IT1 External Interrupt 1 (IE1) Trigger Type.
Set by software to specify edge-sensitive detection (i.e., 1-to-0 transition).
Cleared by software to specify level-sensitive detection (i.e., zero level).
1 IE0 External Interrupt 0 ( INT0) Flag.
Set by hardware by a falling edge or zero level being applied to external interrupt pin INT0,
depending on bit IT0 state.
Cleared by hardware when the PC vectors to the interrupt service routine only if the interrupt
was transition-activated. If level-activated, the external requesting source controls the request
flag, rather than the on-chip hardware.
0 IT0 External Interrupt 0 (IE0) Trigger Type.
Set by software to specify edge-sensitive detection (i.e., 1-to-0 transition).
Cleared by software to specify level-sensitive detection (i.e., zero level).
Timer/Counter 0 and 1 Data Registers
Each timer consists of two 8-bit registers. These can be used as
independent registers or combined to be a single 16-bit register
depending on the timer mode configuration.
TH0 and TL0
Timer 0 high byte and low byte.
SFR Address = 8CH, 8AH respectively.
TH1 and TL1
Timer 1 high byte and low byte.
SFR Address = 8DH, 8BH respectively.
TCON: Timer/Counter 0 and 1 Control Register
SFR Address
88H
Power-On Default Value 00H
Bit Addressable Yes