I2c compatible interface, Aduc812 – Analog Devices ADuC812 User Manual
Page 28
REV. B
ADuC812
–28–
I
2
C-COMPATIBLE INTERFACE
The ADuC812 supports a 2-wire serial interface mode which is
I
2
C compatible. The I
2
C-compatible interface shares its pins with
the on-chip SPI interface and therefore the user can only enable
one or the other interface at any given time (see SPE in SPICON
previously). An Application Note describing the operation of this
interface as implemented is available from the MicroConverter
Website at www.analog.com/microconverter. This interface
can be configured as a Software Master or Hardware Slave,
and uses two pins in the interface.
SDATA (Pin 27)
Serial data I/O Pin
SCLOCK (Pin 26)
Serial Clock
Three SFRs are used to control the I
2
C-compatible interface.
These are described below:
I2CCON:
I
2
C Control Register
SFR Address
E8H
Power-On Default Value
00H
Bit Addressable
Yes
O
D
M
E
D
M
O
C
M
I
D
M
M
C
2
I
S
R
C
2
I
X
T
C
2
I
I
C
2
I
Table XIII. I2CCON SFR Bit Designations
Bit
Name
Description
7
MDO
I
2
C Software Master Data Output Bit (MASTER MODE ONLY).
This data bit is used to implement a master I
2
C transmitter interface in software. Data written to this
bit will be outputted on the SDATA pin if the data output enable (MDE) bit is set.
6
MDE
I
2
C Software Master Data Output Enable Bit (MASTER MODE ONLY).
Set by user to enable the SDATA pin as an output (Tx). Cleared by the user to enable SDATA pin
as an input (Rx).
5
MCO
I
2
C Software Master Clock Output Bit (MASTER MODE ONLY).
This data bit is used to implement a master I
2
C transmitter interface in software. Data written to
this bit will be outputted on the SCLOCK pin.
4
MDI
I
2
C Software Master Data Input Bit (MASTER MODE ONLY).
This data bit is used to implement a master I
2
C receiver interface in software. Data on the SDATA
pin is latched into this bit on SCLOCK if the Data Output Enable (MDE) = “0.”
3
I2CM
I
2
C Master/Slave Mode Bit.
Set by user to enable I
2
C software master mode.
Cleared by user to enable I
2
C hardware slave mode.
2
I2CRS
I
2
C Reset Bit (SLAVE MODE ONLY).
Set by user to reset the I
2
C interface.
Cleared by user code for normal I
2
C operation.
1
I2CTX
I
2
C Direction Transfer Bit (SLAVE MODE ONLY).
Set by the MicroConverter if the interface is transmitting.
Cleared by the MicroConverter if the interface is receiving.
0
I2CI
I
2
C Interrupt Bit (SLAVE MODE ONLY).
Set by the MicroConverter after a byte has been transmitted or received.
Cleared by User Software.
I2CADD
I
2
C Address Register
Function
Holds the I
2
C peripheral address
for the part. It may be overwritten
by user code. Technical Note
µC001
at www.analog.com/microconverter
describes the format of the I
2
C
standard 7-bit address in detail.
SFR Address
9BH
Power-On Default Value
55H
Bit Addressable
No
I2CDAT
I
2
C Data Register
Function
The I2CDAT SFR is written by
the user to transmit data over
the I
2
C interface or read by user
code to read data just received by
the I
2
C interface. User software
should only access I2CDAT once
per interrupt cycle.
SFR Address
9AH
Power-On Default Value
00H
Bit Addressable
No