Analog Devices ADuC812 - Manual (Page 41)

REV. B
ADuC812
–41–
If access to more than 64K bytes of RAM is desired, a feature
unique to the ADuC812 allows addressing up to 16M bytes
of external RAM simply by adding an additional latch as illustrated
in Figure 39.
LATCH
ADuC812
RD
P2
ALE
P0
WR
LATCH
SRAM
OE
A8–A15
A0–A7
D0–D7
(DATA)
WE
A16–A23
Figure 39. External Data Memory Interface (16 M Bytes
Address Space)
In either implementation, Port 0 (P0) serves as a multiplexed
address/data bus. It emits the low byte of the data pointer (DPL) as
an address, which is latched by a pulse of ALE prior to data being
placed on the bus by the ADuC812 (write operation) or the
SRAM (read operation). Port 2 (P2) provides the data pointer
page byte (DPP) to be latched by ALE, followed by the data
pointer high byte (DPH). If no latch is connected to P2, DPP is
ignored by the SRAM, and the 8051 standard of 64K byte external
data memory access is maintained.
Detailed timing diagrams of external program and data memory
read and write access can be found in the timing specification
sections of this data sheet.
Power-On Reset Operation
External POR (power-on reset) circuitry must be implemented to
drive the RESET pin of the ADuC812. The circuit must hold
the RESET pin asserted (high) whenever the power supply
(DV
DD
) is below 2.5 V. Furthermore, V
DD
must remain above
2.5 V for at least 10 ms before the RESET signal is deasserted
(low) by which time the power supply must have reached at least
a 2.7 V level. The external POR circuit must be operational
down to 1.2 V or less. The timing diagram of Figure 40 illus-
trates this functionality under three separate events: power-up,
brownout, and power-down. Notice that when RESET is asserted
(high) it tracks the voltage on DV
DD
. These recommendations
must be adhered to through the manufacturing flow of your
ADuC812-based system as well as during its normal power-on
operation. Failure to adhere to these recommendations can
result in permanent damage to device functionality.
10ms
MIN
1.2V MAX 10ms
MIN
2.5V MIN
1.2V MAX
DV DD
RESET
Figure 40. External POR Timing
The best way to implement an external POR function to meet the
above requirements involves the use of a dedicated POR chip, such
as the ADM809/ADM810 SOT-23 packaged PORs from Analog
Devices. Recommended connection diagrams for both active-high
ADM810 and active-low ADM809 PORs are shown in Figure
41 and Figure 42, respectively.
DV
DD
RESET
48
34
20
15
ADuC812
POR
(ACTIVE HIGH)
POWER SUPPLY
Figure 41. External Active High POR Circuit
Some active-low POR chips, such as the ADM809 can be used with
a manual push-button as an additional reset source as illustrated
by the dashed line connection in Figure 42.
DV
DD
RESET
48
34
20
ADuC812
15
OPTIONAL
MANUAL
RESET
PUSH-BUTTON
POR
(ACTIVE LOW)
POWER SUPPLY
1k ⍀
Figure 42. External Active Low POR Circuit
Power Supplies
The ADuC812’s operational power supply voltage range is 2.7 V
to 5.25 V. Although the guaranteed data sheet specifications are
given only for power supplies within 2.7 V to 3.6 V or
±10% of
the nominal 5 V level, the chip will function equally well at any
power supply level between 2.7 V and 5.5 V.
Separate analog and digital power supply pins (AV
DD
and DV
DD
respectively) allow AV
DD
to be kept relatively free of noisy digital
signals often present on the system DV
DD
line. However, though
you can power AV
DD
and DV
DD
from two separate supplies if
desired, you must ensure that they remain within
±0.3 V of one
another at all times in order to avoid damaging the chip (as per the
Absolute Maximum Ratings section of this data sheet). Therefore
it is recommended that unless AV
DD
and DV
DD
are connected
directly together, you connect back-to-back Schottky diodes
between them as shown in Figure 43.
DV
DD
48
34
20
ADuC812
5
6 AGND
AV
DD
–
+
0.1 ␮F
10 ␮F
ANALOG SUPPLY
10 ␮F
DGND 35
21
47
0.1 ␮F
–
+
DIGITAL SUPPLY
Figure 43. External Dual-Supply Connections