IEI Integration KINO-9652 v1.00 - Manual (Page 47)

KINO-9652 Mini-ITX SBC
Page 25
PCI Express Rev 1.0a specification
High bandwidth density per pin
Wide,pipelined internal data path architecture
Optimized transmit (Tx) and receive (Rx) queues
32 KB configurable Rx and Tx first-in/first-out (FIFO)
IEEE 802.3x*-compliant flow-control support with software controllable pause
times and threshold values
Programmable host memory Rx buffers (256 B-16 KB)
Descriptor ring management hardware for Tx and Rx
Mechanism for reducing interrupts from Tx/Rx operations
Integrated PHY for 10/100/1000 Mbps (full- and half-duplex)
IEEE 802.3ab* auto-negotiation support
IEEE 802.3ab PHY compliance and compatibility
Tx/Rx IP,TCP,and UDP checksum offloading
Tx TCP segmentation
IEEE 802.1q* Virtual Local Area Network (VLAN) support with VLAN tag
insertion, stripping, and packet filtering for up to 4096 VLAN tags
Boot ROM Preboot eXecution Environment (PXE) Flash interface support
SDG 3.0,WfM 3.0 and PC2001 compliant
Wake on LAN support
2.8 LPC Bus Components
2.8.1 LPC Bus Overview
The LPC bus is connected to components listed below:
TPM connector
Super I/O chipset
2.8.2 TPM Module
A TPM connector on the KINO-9652 is interfaced to the Intel® ICH8ME through the LPC
bus. The TPM connector is shown in Figure 2-15 below.