Jtag emulation port, Jtag emulation port -8 – Analog Devices EZ-KIT Lite ADSP-21364 User Manual
Page 42
System Architecture
2-8
ADSP-21364 EZ-KIT Lite Evaluation System Manual
Limits to the current and to the interface speed must be taken into consid-
eration when using the expansion interface. The maximum current limit is
dependent on the capabilities of the used regulator. Additional circuitry
can also add extra loading to signals, decreasing their maximum effective
speed.
[
Analog Devices does not support and is not responsible for the
effects of additional circuitry.
JTAG Emulation Port
The JTAG emulation port allows an emulator to access the internal and
external memory of the processor through a 6-pin interface. The JTAG
emulation port of the processor also connects to the USB debugging inter-
face. When an emulator connects to the board at
ZP4
, the USB debugging
interface is disabled. This is not the standard connection of the JTAG
interface.
For information about the standard connection of the interface, see EE-68
published on the Analog Devices Web site. For more information about
the JTAG connector, see
“JTAG Header (ZP4)” on page 2-20
. To learn
more about available emulators, contact Analog Devices (see
).