Analog Devices EZ-KIT Lite ADSP-21364 - Manual (Page 40)

System Architecture
2-6 ADSP-21364 EZ-KIT Lite Evaluation System Manual
To use the DAI for a different purpose, disable any signal driving the DAI
pins, with a switch. See
“Codec Setup Switch (SW7)” on page 2-10 for
how to. In addition, the codec setup switch can route the output signal of
the 12.288 MHz audio oscillator. By default, the signal is used as the mas-
ter clock (
MCLK ) for the AD1835A codec.
All of the DAI signals are available externally via the expansion interface
connectors (
J1–3
), as well as the 0.1” spaced header
P3
. The pinout of the
connectors can be found in “ADSP-21364 EZ-KIT Lite Schematic” on
page B-1 .
SPI Interface
The serial peripheral interface (SPI) of the processor connects to an SPI
flash memory and the AD1835A audio codec. The
FLAG0 pin is used as a
memory select for the SPI flash memory, and the FLAG3 pin—for the
AD1835A’s configuration registers.
The SPI chip select lines for the SPI flash memory and the AD1835A
audio codec connect to the processor via switch
SW8 pins 1 and 3. The
default for SW8 is all positions ON . The switch disables the SPI devices on
the EZ-KIT Lite, enabling the same flag pins be driven on the expansion
interface
All of the SPI signals are available externally via the expansion interface
connectors (
J1–3 ), as well as the 0.1” spaced header P2 . The pinout of the
connectors can be found in “ADSP-21364 EZ-KIT Lite Schematic” on
page B-1 .
FLAG Pins
The processor has four general-purpose IO FLAG pins. Table 2-1 describes
each flag connections.