Rainbow Electronics MAX1329 User Manual

Page 26

MAX1329/MAX1330

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs,
Reference, Voltage Monitors, and Temp Sensor

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Upon a power-on reset, the charge pump is disabled.
Enable the charge pump through the CP/VM Control
register. When the charge pump is in its off state, AV

is isolated from DV

unless the bypass switch is

enabled. To bypass the charge pump and directly con-
nect DV

to AV

, enable (close) the bypass switch

through the CP/VM Control register (see Tables 21 and
22). During the on mode, the charge pump boosts
DV

and regulates the voltage to generate the select-

ed output voltage at AV

. The charge-pump output

voltage selections are 3.0V, 4.0V, or 5.0V.

The charge-pump clock and ADC clock are synchro-
nized from the same master clock. The charge pump
uses a pulse-width-modulation (PWM) scheme to regu-
late the output voltage. The charge pump supports a
maximum load of 25mA of current to an external device
including what is required for internal circuitry.

Power Modes

Three power modes are available for the MAX1329/
MAX1330: shutdown, sleep, and normal operation. In shut-
down mode, all functional blocks are powered down except
the serial interface, data registers, and wake-up circuitry (if
enabled). Sleep mode is identical to shutdown mode
except the DV

voltage monitors (if enabled) remain

active. Global sleep or shutdown mode is initiated through a

DPIO configured as

SLP or SHDN inputs. In normal mode,

each analog and digital block can be powered up or shut
down individually through its respective control register.

Voltage Supervisors

The MAX1329/MAX1330 provide two programmable volt-
age supervisors, one for DV

and one for AV

. The

voltage supervisor has two thresholds (set to 1.8V

and 2.7V by default) that are both enabled after a power-
on reset. On initial power-up,

RST1 is assigned the 1.8V

monitor output and

RST2 is assigned the 2.7V monitor

output, both for DV

. If DV

falls below the 1.8V or

2.7V threshold, the VM1A bit or VM1B bit, respectively, in
the Status register is set. The VM1A and VM1B status
bits can also be mapped to the interrupt generator.
The default states of

RST1 and RST2 are open-drain

outputs but can be programmed as push-pull Status
register interrupts through the CP/VM Control register.

The AV

voltage supervisor provides three program-

mable thresholds. If AV

falls below the programmed

threshold, the VM2 bit is set in the Status register. The
VM2 status bit can also be mapped to the interrupt
generator.

Interrupt Generator

The interrupt generator accepts inputs from other internal
circuits to provide an interrupt to an external microcontroller
(µC). The sources for generating an interrupt are program-
mable through the serial interface. Possible sources
include a rising or falling edge on the digital and analog
programmable inputs, ADC alarms, an ADC conversion
complete, an ADC FIFO full, an ADC accumulator full, and
the voltage-supervisor outputs. The interrupt causes

RST1

and/or

RST2 to assert when configured as an interrupt out-

put. The interrupt remains asserted until the Status register
is read. See the CP/VM Control register for programming
the

RST1 and RST2 outputs as interrupts and the Interrupt

Mask register for programming the interrupt sources.

Internal Oscillator and Programmable

Clock Dividers

The MAX1329/MAX1330 feature an internal oscillator,
which operates at a fixed frequency of 3.6864MHz. When
enabled, the internal oscillator provides the master clock
source for the ADC and charge pump. To allow external
devices to use the internally generated clock, configure
CLKIO as an output through the Clock Control register.
The CLKIO output frequency is configurable for
0.9216MHz, 1.8432MHz, and 3.6864MHz. When the inter-
nal oscillator is enabled, and regardless of the CLKIO out-
put frequency, the ADC and charge-pump clock dividers
always receive a 3.6864MHz clock signal (see Figure 3).
After a power-on reset, CLKIO defaults to an output with
the divider set to 2 (resulting in 1.8432MHz).

INTERNAL

OSCILLATOR

4.9152MHz

(OFF, ON)

CLOCK INPUT

DIVIDER

(OFF, /1, /2, /4)

OSCE = 0

CLOCK OUTPUT

DIVIDER

(OFF, /1, /2, /4)

OSCE = 1

CHARGE-PUMP

CLOCK DIVIDER

(/32, /64, /128, /256)

ADC

(ACQUIRE CLKS)

(ADC CONTROL)

(ADC SETUP)

CLKIO

SCLK

MUX

OSCE

MUX

CHARGE PUMP
(OFF, 3V, 4V, 5V)

ADC CLOCK

DIVIDER

(/1, /2, /4, /8)

Figure 3. Clock-Divider Block Diagram