Rainbow Electronics DS2181A - Manual (Page 17)

DS2181A
041995 17/32
TRANSMIT SIGNALLING TIMESLOT TIMING Figure 14
TCLK
TCHCLK
TSTS
TIMESLOT 15 TIMESLOT 16 TIMESLOT 17
RECEIVE SIGNALLING
Receive signalling data is available at two outputs:
RSER and RSD. RSER outputs the signalling data in
timeslot 16 at RSER. The signalling data is also ex- tracted from timeslot 16 and presented at RSD during
the timeslots shown in Table 7. This channel-associated
signalling simplifies CAS system design.
RECEIVE SIGNALLING Table 7
FRAME # RSD 1 VALID DURING
TIMESLOT #
0 15, -2
1 -2 ,17
2 1,18
3 2,19
4 3,20
5 4,21
6 5,22
7 6,23
8 7,24
9 8,25
10 9,26
11 10,27
12 11,28
13 12,29
14 13,30
15 14,31
NOTES: (Applicable only to CAS systems.)
1. RSD is valid for the least significant nibble in each indicated timeslot. Timeslot A data appears in bit 5, B in bit
6, C in bit 7 and D in bit 8.
2. RSD does not output valid data during timeslots 0 and 16.