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Transmit plcp formatter features, Generation of bip-8 (b1), febe and rai (g1), Transmit ds3/e3 formatter features – Rainbow Electronics DS3164 User Manual

Page 8: B3zs/hdb3 encoding, Built-in support for subrate ds3/e3, Hdlc controller features, Byte receive and transmit fifos, Feac controller features, Trail trace buffer features

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Maxim/Dallas Semiconductor Confidential

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• Counters for number of packets and bytes read from the transmit FIFO

3.12 Transmit PLCP Formatter Features

• Insertion of FAS bytes (A1, A2), path overhead identification (POI) bytes, and path overhead bytes

• Generation of BIP-8 (B1), FEBE and RAI (G1)
• C1 cycle/stuff counter generation referenced to the 8KREFI input pin, referenced to the received

PLCP timing, or based on a fixed stuff pattern

• Automatic or manual insertion of FAS errors, BIP-8 errors

• All path overhead fields can be sourced from the PLCP transmit overhead port

3.13 Transmit DS3/E3 Formatter Features

• Insertion of framing overhead for M23 or C-bit parity DS3, G.751 E3 or G.832 E3

• B3ZS/HDB3 encoding
• Generation of RDI, AIS, DS3 idle signal, and G.832-E3 RDI

• Automatic or manual insertion of bipolar violations (BPVs), excessive zeroes (EXZ) occurrences, F-

bit errors, M-bit errors, FAS errors, P-bit parity errors, CP-bit parity errors, BIP-8 errors, and far end
block errors (FEBE)

• HDLC controller with 256 byte FIFO for DS3 path maintenance data link (PMDL), G.751 national bit

or G.832 NR or GC channels

• FEAC controller for DS3 FEAC channel can be configured to send one codeword, one codeword

continuously, or two different codewords back-to-back to send DS3 Line Loopback commands

• 16-byte Trail Trace Buffer sources the G.832 trail access point identifier

• Insertion of G.832 payload type and timing marker bits from registers

• C bits configurable as payload or overhead; as overhead they can be controlled from registers or the

transmit overhead port

• Most framing overhead fields can be sourced from transmit overhead port

• Formatter pass-through mode for clear channel applications and externally defined frame formats

• Built-in support for subrate DS3/E3

3.14 HDLC Controller Features

• 256-byte receive and transmit FIFOs

• Handles all of the normal Layer 2 tasks including zero stuffing/destuffing, FCS generation/checking,

abort generation/checking, flag generation/detection, and byte alignment

• Programmable high or low water marks for the transmit and receive FIFOs

• Terminates the Path Maintenance Data Link in DS3 C-bit Parity mode or the G.751 Sn bit or the

G.832 NR or GC channels

3.15 FEAC Controller Features

• Designed to handle multiple FEAC codewords without Host intervention

• Receive FEAC automatically validates incoming codewords and stores them in a 4-codeword FIFO

• Transmit FEAC can be configured to send one codeword, one codeword continuously, or two

different codewords back-to-back to send DS3 Line Loopback commands

• Terminates the FEAC channel in DS3 C-Bit Parity mode or the Sn bit in E3 mode

3.16 Trail Trace Buffer Features

• Extraction and storage of the incoming G.832 trail access point identifier in a 16-byte receive register