Rainbow Electronics DS3164 - Manual (Page 5)

Maxim/Dallas Semiconductor Confidential Product Preview: DS3161,2,3,4
Rev 1.6 5 of 12 022604
3 FEATURE DETAILS
3.1 Global Features
• System interface configurable for UTOPIA 2 / UTOPIA 3 for ATM cell traffic or POS-PHY 2 / POS-
PHY 3 for HDLC or mixed packet/cell traffic
• Supports the following transmission protocols:
• Direct-mapped ATM over DS3 or subrate DS3
• PLCP-mapped ATM over DS3
• Direct-mapped ATM over G.751 E3 or subrate G.751 E3
• PLCP-mapped ATM over G.751 E3
• Direct-mapped ATM over G.832 E3 or subrate G.832 E3
• Direct-mapped ATM over externally-defined frame formats up to 52 Mbps
• Clear-channel ATM (cell-based physical layer) line rates up to 52 Mbps
• Direct-mapped HDLC over DS3 or subrate DS3
• Direct-mapped HDLC over G.751 E3 or subrate G.751 E3
• Direct-mapped HDLC over G.832 E3 or subrate G.832 E3
• Direct-mapped HDLC over externally-defined frame formats up to 52 Mbps
• Clear-channel HDLC at any line rate up to 52 Mbps
• In UTOPIA bus mode, ports are independently configurable for any ATM protocol
• In POS-PHY bus mode, ports are independently configurable for any ATM or HDLC protocol
• Provides all necessary I/O to support externally controlled subrate DS3 or E3 on any ports
• LIU interface can be AMI logic (POS/NEG/CLK) or binary (DAT/CLK/LCV)
• Supports gapped 52 MHz clock rates for signals embedded in SONET/SDH
• Clock, data and control signals can be inverted to allow a glueless interface to other devices
• Programmable I/O pins (two per port) can be used to control neighboring LIUs (DS3/E3 setting, LBO
setting, etc.)
• Detection of loss of transmit clock and loss of receive clock
• Manual or automatic one-second update of performance monitoring counters
• Each port can be put into a low-power standby mode when not being used
3.2 Receive DS3/E3 Framer Features
• Frame synchronization for M23 or C-bit Parity DS3, G.751 E3 or G.832 E3
• B3ZS/HDB3 decoding
• Detection and accumulation of bipolar violations (BPV), code violations (CV), excessive zeroes
occurrences (EXZ), F-bit errors, M-bit errors, FAS errors, LOF occurrences, P-bit parity errors, CP-
bit parity errors, BIP-8 errors, and far end block errors (FEBE)
• Detection of RDI, AIS, DS3 idle signal, loss of signal (LOS), severely error framing event (SEFE),
change of frame alignment (COFA), receipt of B3ZS/HDB3 codewords, DS3 application ID bit, DS3
M23/C-bit format mismatch, G.751 national bit, and G.832 RDI (FERF), payload type, and timing
marker bits
• HDLC controller with 256 byte FIFO for DS3 path maintenance data link (PMDL), G.751 national bit
or G.832 NR/GC channels
• FEAC controller with four-codeword FIFO for DS3 FEAC channel
• 16-byte Trail Trace Buffer compares and stores G.832 trail access point identifier
• C bits configurable as payload or overhead
• Most framing overhead fields presented on the receive overhead port