Rainbow Electronics AT83C24NDS - Manual (Page 12)

12
4234F–SCR–10/05
AT83C24
Figure 6. Clock Block Diagram with Software Activation (see page 14)
Figure 7. Clock Block Diagram with Hardware Activation (see page 14)
CRST Controller The CRST output pin is driven by the A1/RST pin signal pin or by the CARDRST bit value. This
selection depends of the CRST_SEL bit value (see CONFIG4 register).
If the CRST pin signal is driven by the CARDRST bit value, two modes are available:
• If the ART bit is reset, CRST pin is driven by CARDRST bit.
• If the ART bit is set, CRST pin is controlled and follows the “Automatic Reset Transition”
(page 15).
DCK[2:0]
CKS[2:0]
CLK
A2/CK CCLK
DC/DC
DCCLK
0
1
CKSTOP bit
CARDCK bit
DCK[2:0]
CKS[2:0]
CLK
A2/CK CCLK
DC/DC
DCCLK
0
1
CKSTOP bit
CARDCK bit
CMDVCC
A1/RST
CRST_SEL bit
Hardware
activation