Rainbow Electronics MAX17480 - Manual (Page 40)

MAX17480
AMD 2-/3-Output Mobile Serial
VID Controller
40 ______________________________________________________________________________________
When using low-capacity ceramic filter capacitors,
capacitor size is usually determined by the capacity
needed to prevent V
SOAR from causing problems during
load transients. Generally, once enough capacitance is
added to meet the overshoot requirement, undershoot at
the rising load edge is no longer a problem.
Core Input Capacitor Selection
The input capacitor must meet the ripple-current
requirement (I
RMS ) imposed by the switching currents.
For a dual 180 ° interleaved controller, the out-of-phase
operation reduces the RMS input ripple current, effec-
tively lowering the input capacitance requirements.
When both outputs operate with a duty cycle less than
50% (V
IN
> 2V
OUT
), the RMS input ripple current is
defined by the following equation:
where I IN is the average input current:
In combined mode (GNDS1 = V DDIO or GNDS2 =
V DDIO ) with both phases active, the input RMS current
simplifies to:
For most applications, nontantalum chemistries (ceram-
ic, aluminum, or OS-CON) are preferred due
to their resistance to inrush surge currents typical of
systems with a mechanical switch or connector in
series with the input. If the MAX17480 is operated as
the second stage of a two-stage power-conversion sys-
tem, tantalum input capacitors are acceptable. In either
configuration, choose an input capacitor that exhibits
less than +10
°C temperature rise at the RMS input cur-
rent for optimal circuit longevity.
Core Voltage Positioning and Loop Compensation
Voltage positioning dynamically lowers the output volt-
age in response to the load current, reducing the output
capacitance and processor’s power-dissipation require-
ments. The controller uses a transconductance amplifier
to set the transient AC and DC output-voltage droop
(Figure 5). The FBAC and FBDC configuration adjusts
the steady-state regulation voltage as a function of the
load. This adjustability allows flexibility in the selected
current-sense resistor value or inductor DCR, and allows
smaller current-sense resistance to be used, reducing
the overall power dissipated.
Core Transient Droop and Stability
The inductor current ripple sensed across the current-
sense inputs (CSP_ - CSN_) generates a proportionate
current out of the FBAC pin. This AC current flowing
across the effective impedance at FBAC generates an
AC ripple voltage. Actual stability, however, depends
on the AC voltage at the FBDC pin, and not on the
FBAC pin. Based on the configuration shown in Figure
5, the ripple voltage at the FBDC pin can only be less
than, or equal to, the ripple at the FBAC pin.
With the requirement that R FBDC = R FBAC , and
(Z CFB //R FB ) < 10% of R FBAC , then:
where G m(FBAC_) is typically 2mS as defined in the
Electrical Characteristics table, R SENSE_ is the effective
value of the current-sense element that is used to pro-
vide the (CSP_, CSN_) current-sense voltage, and f
SW
is the selected switching frequency.
Based on the above requirement for R FBAC and R FBDC ,
and with the other requirement for R
FBDC
defined in the
Core Steady-State Voltage Positioning (DC Droop) sec-
tion, R FBAC and R FBDC can be chosen. The resultant
AC droop is:
Capacitor C FB is required when the R DROOP_DC is less
than R DROOP_AC . Choose C FB according to the following
equation:
Core Steady-State Voltage Positioning
With R DROOP_AC defined, the steady-state voltage-
positioning slope, R DROOP_DC , can only be less than,
or at most equal to, R
DROOP_AC
:
Choose the R FBDC and R FBAC already previously cho-
sen, then select R FB to give the desired droop.
DC droop is typically used together with the +12.5mV
offset feature to keep within the DC tolerance window of
the application. See the
Offset and Address Change for
Core SMPSs (OPTION) section.
R
R R R
R R R
G
DROOP DC
FBDC FBAC SENSE
FBAC FBDC FB
m _
=
+ + (( ) FBAC
C R R R t
FB FB FBAC FBDC SW
Ч + ⎡⎣ ⎤⎦ = Ч / /( ) 3
R
R R R
R R
G
DROOP AC
FBDC FBAC SENSE
FBAC FBDC
m FBA _ (
≈
+ C C)
R R
C f R G
FBAC FBDC
OUT SW SENSE m FBAC
= ≥
1
_ ( )
I I
V
V
V
V
RMS OUT
OUT
IN
OUT
IN
=
⎛
⎝
⎜
⎞
⎠
⎟ −
⎛
⎝
⎜
⎞
⎠
⎟
1
2
I
V
V
I
V
V
I
IN
OUT
IN
OUT
OUT
IN
OUT
=
⎛
⎝⎜ ⎞
⎠⎟
+
⎛
⎝⎜ ⎞
⎠⎟
1
1
2
2
I
V
V
I I I
V
V
RMS
OUT
IN
OUT OUT IN
OUT
I
=
⎛
⎝⎜ ⎞
⎠⎟
−
( )
+ 1
1 1
2
N N
OUT OUT IN
I I I
⎛
⎝⎜ ⎞
⎠⎟
−
( )
2 2