Rainbow Electronics MAX17480 - Manual (Page 36)

MAX17480
AMD 2-/3-Output Mobile Serial
VID Controller
36 ______________________________________________________________________________________
Fault Protection (Latched)
Output Overvoltage Protection (OVP)
The overvoltage protection (OVP) circuit is designed to
protect the CPU against a shorted high-side MOSFET
by drawing high current and blowing the battery fuse.
The MAX17480 continuously monitors the output for an
overvoltage fault. The controller detects an OVP fault if
the output voltage exceeds the set VID DAC voltage by
more than 300mV. The OVP threshold tracks the VID
DAC voltage except during a downward VID transition.
During a downward VID transition, the OVP threshold is
set at 1.85V (typ) until the output reaches regulation,
when the OVP threshold is reset back to 300mV above
the VID setting.
When the OVP circuit detects an overvoltage fault in
core SMPSs, it immediately sets the fault latch and
forces the external low-side driver high on the faulted
SMPS. The nonfaulted SMPSs are also shut down by
turning on the internal passive discharge MOSFET. The
synchronous-rectifier MOSFETs of the faulted side are
turned on with 100% duty, which rapidly discharges the
output filter capacitor and forces the output low. If the
condition that caused the overvoltage (such as a short-
ed high-side MOSFET) persists, the battery fuse blows.
Toggle SHDN or cycle the V
CC power supply below
0.5V to clear the fault latch and reactivate the controller.
When the core SMPSs are configured in combined mode,
the synchronous-rectifier MOSFETs of both phases are
turned on with 100% duty in response to an overvoltage
fault. Passive shutdown is initiated for the NB SMPS.
The NB SMPS has no OVP.
Output Undervoltage Protection (UVP)
If any of the MAX17480 output voltages are 400mV
below the target voltage, the controller sets the fault
latch, shuts down all the SMPSs, and activates the
internal passive discharge MOSFET. Toggle SHDN or
cycle the V
CC
power supply below 0.5V to clear the
fault latch and reactivate the controller.
V CC Undervoltage-Lockout (UVLO) Protection
If the V CC voltage drops below 4.2V (typ), the controller
assumes that there is not enough supply voltage to
make valid decisions and sets a fault latch. During a
UVLO fault, the controller shuts down all the SMPSs
immediately, forces DL and DH low, and pulls CSN1,
CSN2, and OUT3 low through internal 20
Ω discharge
FETs. If the V CC falls below the POR threshold (1.8V,
typ), DL is forced low even if it was previously high due
to a latched overvoltage fault.
Toggle SHDN or cycle the V CC power supply below
0.5V to clear the fault latch and reactivate the controller.
V DDIO Undervoltage-Lockout (UVLO) Protection
If the V
DDIO
voltage drops below 0.7V (typ), the con-
troller assumes that there is not enough supply voltage
to make valid decisions and sets a UV fault latch.
During V
DDIO UVLO, as with UVP, the controller shuts
down all the SMPSs immediately, forces DL and DH
low, and pulls CSN1, CSN2, and OUT3 low through
internal 20
Ω discharge FETs. If the V
CC
falls below the
POR threshold (1.8V, typ), DL is forced low even if it
was previously high due to a latched overvoltage fault.
Toggle SHDN or cycle the V
CC
power supply below
0.5V to clear the fault latch and reactivate the controller.
Thermal Fault Protection
The MAX17480 features a thermal fault protection
circuit. When the junction temperature rises above
+160
°C, a thermal sensor sets the fault latch and shuts
down immediately, forcing DH and DL low and turning
on the 20
Ω discharge FETs for all SMPSs. Toggle
SHDN or cycle the V
CC power supply below 0.5V to
clear the fault latch and reactivate the controller after
the junction temperature cools by 15
°C.
Other Fault Protection (Nonlatched)
V
IN3
Undervoltage-Lockout (UVLO) Protection
If the V
IN3
voltage drops below 2.5V (typ), the controller
assumes that there is not enough input voltage for NB
SMPSs. If V
IN3 UVLO happens before or just after soft-
start, the NB SMPS is disabled and the internal target
voltage stays off. When the V
IN3 subsequently rises past
its UVLO rising threshold 2.6V (typ), NB goes through the
soft-start sequence with a 1mV/µs slew rate.
If V IN3 UVLO happens while the MAX17480 is running,
the NB SMPS is stopped, the NB target is reset to 0
immediately, and PWRGD is forced low. When V
IN3
subsequently rises above the UVLO rising threshold
2.6V (typ), the NB SMPS restarts with 1mV/µs slew rate
to the previous DAC target.
Core SMPS MOSFET Gate Drivers
The DH and DL drivers are optimized for driving moder-
ate-sized high-side and larger low-side power
MOSFETs. This is consistent with the low duty factor
seen in notebook applications where a large V
IN - V OUT
differential exists. The high-side gate drivers (DH)
source and sink 2.2A, and the low-side gate drivers
(DL) source 2.7A and sink 8A. This ensures robust gate
drive for high-current applications. The DH floating
high-side MOSFET drivers are powered by internal
boost switch charge pumps at BST, while the DL syn-
chronous-rectifier drivers are powered directly by the
5V bias supply (V
DD ).