Rainbow Electronics MAX17480 - Manual (Page 30)

MAX17480
AMD 2-/3-Output Mobile Serial
VID Controller
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depending on the external MOSFETs and switching fre-
quency. To maintain high efficiency under light load
conditions, the processor could switch the controller to a
low-power pulse-skipping control scheme.
Pulse-Skipping Operation
During soft-start and in power-saving mode—when the
PSI_L bit is set to 0—the MAX17480 operates in pulse-
skipping mode. Pulse-skipping mode enables the driver’s
zero-crossing comparator, so the driver pulls its DL low
when “zero” inductor current is detected (V
GND - V LX =
0). This keeps the inductor from discharging the output
capacitors and forces the controller to skip pulses under
light load conditions to avoid overcharging the output.
In pulse-skipping operation, the controller terminates
the on-time when the output voltage exceeds the feed-
back threshold and when the current-sense voltage
exceeds the idle-mode current-sense threshold (V
IDLE
= 0.15 x V LIMIT for the core SMPS and I LX3MIN = 0.25 x
I LX3PK setting for the NB SMPS). Under heavy load
conditions, the continuous inductor current remains
above the idle-mode current-sense threshold, so the
on-time depends only on the feedback voltage thresh-
old. Under light load conditions, the controller remains
above the feedback voltage threshold, so the on-time
duration depends solely on the idle-mode current-
sense threshold, which is approximately 15% of the full-
load peak current-limit threshold set by ILIM12 for the
core SMPSs and 25% of the full-load peak current-limit
threshold set by ILIM3 for the NB SMPS.
During downward VID transitions, the controller tem-
porarily sets the OVP threshold of the SMPSs to 1.85V
(typ), preventing false OVP faults. Once the error ampli-
fier detects that the output voltage is in regulation, the
OVP threshold tracks the selected VID DAC code.
Each SMPS can be individually set to operate in pulse-
skipping mode when its PSI_L bit is set to 0, or set to oper-
ate in forced-PWM mode when its PSI_L bit is set to 1.
When the core SMPSs are configured for combined-
mode operation, core supplies operate in 1-phase
pulse-skipping mode when PSI_L = 0, and core sup-
plies are in 2-phase forced-PWM mode when PSI_L = 1.
Idle-Mode Current-Sense Threshold
The idle-mode current-sense threshold forces a lightly
loaded SMPS to source a minimum amount of power
with each on-time since the controller cannot terminate
the on-time until the current-sense voltage exceeds the
idle-mode current-sense threshold (V
IDLE = 0.15 x
V LIMIT for the core SMPS and I LX3MIN = 0.25 x I LX3PK
setting for the NB SMPS). Since the zero-crossing com-
parator prevents the switching SMPS from sinking
current, the controller must skip pulses to avoid over-
charging the output. When the clock edge occurs, if the
output voltage still exceeds the feedback threshold, the
controller does not initiate another on-time. This forces
the controller to actually regulate the valley of the out-
put voltage ripple under light load conditions.
Automatic Pulse-Skipping Crossover
In skip mode, the MAX17480 zero-crossing compara-
tors are active. Therefore, an inherent automatic
switchover to PFM takes place at light loads, resulting in
a highly efficient operating mode. This switchover is
affected by a comparator that truncates the low-side
switch on-time at the inductor current’s zero crossing.
The driver’s zero-crossing comparator senses the
inductor current across the low-side MOSFET. Once
V
GND - V LX drops below the zero-crossing threshold,
the driver forces DL low. This mechanism causes the
threshold between pulse-skipping PFM and nonskipping
PWM operation to coincide with the boundary between
continuous and discontinuous inductor-current opera-
tion (also known as the critical conduction point). The
load-current level at which the PFM/PWM crossover
occurs, I
LOAD(SKIP) , is given by:
The switching waveforms can appear noisy and asyn-
chronous when light loading causes pulse-skipping
operation, but this is a normal operating condition that
results in high light-load efficiency. Trade-off in PFM
noise vs. light-load efficiency is made by varying the
inductor value. Generally, low inductor values produce a
broader efficiency vs. load curve, while higher values
result in higher full-load efficiency (assuming that the coil
resistance remains fixed) and less output voltage ripple.
Penalties for using higher inductor values include larger
physical size and degraded load-transient response
(especially at low input-voltage levels).
Current Sense
Core SMPS Current Sense
The output current of each phase is sensed differentially.
A low offset voltage and high-gain differential current
amplifier at each phase allows low-resistance current-
sense resistors to be used to minimize power dissipa-
tion. Sensing the current at the output of each phase
offers advantages, including less noise sensitivity, more
accurate current sharing between phases, and the flex-
ibility of using either a current-sense resistor or the DC
resistance of the output inductor.
I
V V V
V f L
LOAD SKIP
OUT IN OUT
IN SW
( )
=
− ( )
2