Rainbow Electronics MAX17480 - Manual (Page 27)

MAX17480
AMD 2-/3-Output Mobile Serial
VID Controller
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where V CS = V CSP - V CSN is the differential current-
sense voltage, and G m(FBAC) is 2.06mS (max) as
defined in the Electrical Characteristics table.
AC droop is required for stable operation of the
MAX17480. A minimum of 1.5mV/A is recommended.
AC droop must not be disabled.
Core Differential Remote Sense
The MAX17480 controller includes independent differen-
tial, remote-sense inputs for each CPU core to eliminate
the effects of voltage drops along the PCB traces and
through the processor’s power pins. The feedback-sense
(FBDC_) input connects to the remote-sensed output
through the resistance at FBDC_ (R
FBDC_ ). The ground-
sense (GNDS_) input connects to an amplifier that adds
an offset directly to the target voltage, effectively
adjusting the output voltage to counteract the voltage
drop in the ground path. Connect the feedback-sense
(FBDC_) R
FBDC_ resistor and ground-sense (GNDS_)
input directly to the respective CPU core’s remote-
sense outputs as shown in Figure 2.
GNDS1 and GNDS2 are dual-function pins. At power-on,
the voltage levels on GNDS1 and GNDS2 configure the
MAX17480 as two independent switching SMPSs, or one
higher current 2-phase SMPS. Keep both GNDS1 and
GNDS2 low during power-up to configure the MAX17480
in separate mode. Connect GNDS1 or GNDS2 to a volt-
age above 0.8V (typ) for combined-mode operation. In
the AMD mobile system, this is automatically done by the
CPU that is plugged into the socket that pulls GNDS1 or
GNDS2 the V
DDIO voltage level.
When GNDS1 is pulled high to indicate combined-
mode operation, the remote ground sense is automati-
cally switched to GNDS2. When GNDS2 is pulled high
to indicate combined-mode operation, the remote
ground sense is automatically switched to GNDS1.
GNDS1 and GNDS2 do not dynamically switch in the
real application. It is only switched when one CPU is
removed (e.g., split-core CPU), and another is plugged
in (e.g., combined-core CPU). This should not be done
when the socket is “hot” (i.e., powered).
The MAX17480 checks the GNDS1 and GNDS2 levels
at the time when the internal REFOK signal goes high,
and latches the operating mode information (separate
or combined mode). This latch is cleared by cycling the
SHDN pin.
Core Integrator Amplifier
An internal integrator amplifier forces the DC average of
the FBDC_ voltage to equal the target voltage. This
transconductance amplifier integrates the feedback
voltage and provides a fine adjustment to the regulation
voltage (Figure 4), allowing accurate DC output-voltage
regulation regardless of the output ripple voltage.
The MAX17480 disables the integrator during down-
ward VID transitions done in pulse-skipping mode. The
integrator remains disabled until the transition is com-
pleted (the internal target settles) and the output is in
regulation (edge detected on the error comparator).
The integrator amplifier can shift the output voltage by
±80mV (min). The maximum difference between tran-
sient AC droop and DC droop should not exceed
±80mV at the maximum allowed load current to guaran-
tee proper DC output-voltage accuracy over the full
load conditions.
NB SMPS Feedback Adjustment Amplifiers
NB Steady-State Voltage Positioning (DC Droop)
The NB SMPS has a built-in load-line that is -5.5mV/A.
The output peak voltage (V
OUT3_PK+ ) is set to:
where the target voltage (V TARGET3 ) is defined in the
Nominal Output-Voltage Selection section, f
SW3
is the
NB switching frequency, and I LOAD3 is the output load
current of the NB SMPS.
2-Wire Serial Interface (SVC, SVD)
The MAX17480 supports the 2-wire, write-only, serial-
interface bus as defined by the AMD serial VID inter-
face specification. The serial interface is similar to the
high-speed 3.4MHz I
2 C bus, but without the master
mode sequence. The bus consists of a clock line (SVC)
and a data line (SVD). The CPU is the bus master, and
the MAX17480 is the slave. The MAX17480 serial inter-
face works from 100kHz to 3.4MHz. In the AMD mobile
application, the bus runs at 3.4MHz.
The serial interface is active only after PGD_IN goes
high in the startup sequence. The CPU sets the VID
voltage of the three internal DACs and the PSI_L bit
through the serial interface.
During the startup sequence, the SVC and SVD inputs
serve an alternate function to set the 2-bit boot VID for
all three DACs while PWRGD is low.
V V mV/A (I
I
OUT3_PK TARGET3 LOAD3
L
= − × +
5 5
3
2
. )
∆
∆
I
L
3 3
=
−
( )
Ч
Ч Ч
V V V
L V f
IN OUT OUT
IN SW
3 3 3
3 3 3
I G V
FBAC m FBAC CS
=
( )