Xilinx ML310 - Manual (Page 23)

ML310 User Guide www.xilinx.com 23
UG068 (v1.01) August 25, 2004 1-800-255-7778
Board Hardware R
ddr_ad[2] AG20 DDR_A2 41
ddr_ad[3] AF23 DDR_A3 130
ddr_ad[4] AH22 DDR_A4 37
ddr_ad[5] AF22 DDR_A5 32
ddr_ad[6] AF21 DDR_A6 125
ddr_ad[7] AH21 DDR_A7 29
ddr_ad[8] AG21 DDR_A8 122
ddr_ad[9] AJ21 DDR_A9 27
ddr_ad[10] AK21 DDR_A10 141
ddr_ad[11] AH20 DDR_A11 118
ddr_ad[12] AF20 DDR_A12 115
ddr_ba[0] AG18 DDR_BA0 59
ddr_ba[1] AF19 DDR_BA1 62
ddr_casb AF17 DDR_CAS_N 65
ddr_cke AG24 DDR_CKE0 21
ddr_csb AE17 DDR_S0_N 157
ddr_rasb AE16 DDR_RAS_N 154
ddr_web AD16 DDR_WE_N 63
ddr_clk V30 DDR_CK0 137
ddr_clkb U30 DDR_CK0_N 138
ddr_clk_fb AF16 DDR_CLK_FB N/A
ddr_clk_fb_out AG25 DDR_CLK_FB N/A
ddr_dm[0] AH29 DDR_DQM07 177
ddr_dm[1] AE29 DDR_DQM06 169
ddr_dm[2] AA24 DDR_DQM05 159
ddr_dm[3] AB30 DDR_DQM04 149
ddr_dm[4] P30 DDR_DQM03 129
ddr_dm[5] M30 DDR_DQM02 119
ddr_dm[6] K24 DDR_DQM01 107
ddr_dm[7] E30 DDR_DQM00 97
ddr_dqs[0] AG30 DDR_DQS07 86
ddr_dqs[1] AF30 DDR_DQS06 78
ddr_dqs[2] AA28 DDR_DQS05 67
ddr_dqs[3] Y29 DDR_DQS04 56
ddr_dqs[4] P28 DDR_DQS03 36
Table 2-1: Connections from FPGA to DIMM Interface, P7
UCF Signal Name
XC2VP30 Pin
(U37)
Schem Signal Name
DIMM
(P7)