Texas Instruments TMS320C642x DSP - Manual (Page 6)

1 Device Clocking
1.1 Overview
1.2 Clock Domains
1.2.1 Core Domains
User's Guide
SPRUES0B – December 2007
Phase-Locked Loop Controller (PLLC)
The C642x DSP requires one primary reference clock. The primary reference clock can be either crystal
input or driven by external oscillators. A 15 to 30 MHZ crystal at the MXI/CLKIN pin is recommended for
the system PLLs, which generate the clocks for the DSP, peripherals, and DMA.
For detailed specifications on clock frequency and voltage requirements, see the device-specific data
manual.
There are two clocking modes:
•
PLL Bypass Mode - power saving (device defaults to this mode)
•
PLL Mode - PLL multiplies input clock up to the desired operating frequency
The clock of the major chip components must be programmed to operate at fixed ratios of the primary
system/DSP clock frequency within each mode, as shown in
Table 1 . The C642x DSP clocking
architecture is shown in Figure 1 .
Table 1. System Clock Modes and Fixed Ratios for Core Clock Domains
Components Core Clock Domain Fixed Ratio vs. DSP frequency
DSP CLKDIV1 1:1
EDMA CLKDIV3 1:3
Peripherals (CLKDIV3 domain) CLKDIV3 1:3
Peripherals (CLKDIV6 domain) CLKDIV6 1:6
The core domains refer to the clock domains for all of the internal processing elements of the C642x DSP,
such as the DSP/EDMA/peripherals, etc. All internal communications between DSP and modules operate
at core domain clock frequencies. All of the core clock domains are synchronous to each other, come from
a single PLL (PLL1), have aligned clock edges, and have fixed divide by ratio requirements, as shown in
Table 1 and Figure 1 . It is user's responsibility to ensure the fixed divide ratios between these core clock
domains are achieved.
The DSP is in the CLKDIV1 domain and receives the PLL1 frequency directly (PLLDIV1 of PLL controller
1 (PLLC1) set to divide by 1), or receives the divided-down PLL1 frequency (PLLDIV1 of PLLC1 set to
divide by 2, 3, etc.). The DSP has internal clock dividers that it uses to create the DSP
÷
3 clock frequency
to communicate with other components on-chip.
Modules in the CLKDIV3 domain (for example, EDMA, CLKDIV3 domain peripherals) must run at 1/3 the
DSP frequency.
6 Phase-Locked Loop Controller (PLLC) SPRUES0B – December 2007
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