Texas Instruments TMS320C642x DSP - Manual (Page 11)

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2 PLL Controller
2.1 PLL Module
PLL Controller
The C642x DSP has two PLLs (PLL1 and PLL2) that provide clocks to different parts of the system. PLL1
provides clocks (though various dividers) to most of the components of the C642x DSP. PLL2 is dedicated
to the DDR2 port. The reference clock is the 15 to 30 MHZ crystal or 1.8V LVCMOS-compatible clock
input, as mentioned in the data manual.
The PLL controller provides the following:
•
Glitch-Free Transitions (on changing clock settings)
•
Domain Clocks Alignment
•
Clock Gating
•
PLL power down
The various clock outputs given by the controller are as follows:
•
Domain Clocks: SYSCLK[1:n]
•
Auxiliary Clock from reference clock source: AUXCLK
•
Bypass Domain clock: SYSCLKBP
•
Observe Clock: OBSCLK
Various dividers that can be used on the C642x DSP are as follows:
•
PLL Controller Dividers (for SYSCLK[1:n]): PLLDIV1, ..., PLLDIVn
•
Bypass Divider (for SYSCLKBP): BPDIV
•
Oscillator Divider (for OBSCLK): OSCDIV1
Various other controls supported are as follows:
•
PLL Multiplier Control: PLLM
•
Software-programmable PLL Bypass: PLLEN
SPRUES0B – December 2007 Phase-Locked Loop Controller (PLLC) 11
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