Texas Instruments TMS320C642x DSP - Manual (Page 17)

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2.3.1 Device Clock Generation
2.3.2 Steps for Changing PLL2 Frequency
2.3.2.1 DDR2 Considerations When Modifying PLL2 Frequency
PLL Controller
PLLC2 generates clocks from the PLL2 output clock for use by the DDR2 memory controller. These are
summarized in
Table 7 .
Table 7. DDR PLLC2 Output Clocks
Output Clock Used by Default Divider
SYSCLK1 DDR Phy /2
SYSCLKBP DDR VTP Controller /2
The SYSCLK1 output clock divider value defaults to /2. Assuming a 25 MHZ MXI/CLKIN and the PLL2
default multiplier of
×
20, this results in a 250 MHZ DDR Phy clock (125 MHZ DDR2). It can be modified by
software (RATIO bit in PLLDIV1) in combination with other PLL multipliers to achieve the desired DDR
clock rate.
The PLLC2 is programmed similarly to the PLLC1. Refer to the appropriate subsection on how to program
the PLL2 clocks:
•
If the PLL is powered down (PLLPWRDN bit in PLLCTL is set to 1), follow the full PLL initialization
procedure in
Section 2.3.2.2 to initialize the PLL.
•
If the PLL is not powered down (PLLPWRDN bit in PLLCTL is cleared to 0), follow the sequence in
Section 2.3.2.3 to change the PLL multiplier.
•
If the PLL is already running at a desired multiplier and you only want to change the SYSCLK dividers,
follow the sequence in
Section 2.3.2.4 .
Note that the PLL is powered down after the following device-level global resets:
•
Power-on Reset (POR)
•
Warm Reset (RESET)
•
Max Reset
In addition, note that the PLL2 frequency directly affects the DDR2 memory controller. The DDR2 memory
controller requires special sequences to be followed before and after you change the PLL2 frequency. You
must follow the additional considerations for the DDR2 memory controller in
Section 2.3.2.1 in order to not
corrupt DDR2 operation.
Before changing PLL2 and/or PLLC2 frequency, you must take into account the DDR2 memory controller
requirements. If the DDR2 memory controller is used in the system, follow the additional steps in this
section to change PLL2 and/or PLLC2 frequency without corrupting DDR2 operation.
•
If the DDR2 memory controller is in reset when you desire to change the PLL2 frequency, follow the
steps in
Example 2 .
•
If the DDR2 memory controller is already out of reset when you desire to change the PLL2 frequency,
follow the steps in
Example 3 .
SPRUES0B – December 2007 Phase-Locked Loop Controller (PLLC) 17
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