Texas Instruments TMS320C642x DSP - Manual (Page 33)

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2.4.16 SYSCLK Status Register (SYSTAT)
PLL Controller
The SYSCLK status register (SYSTAT) is shown in Figure 19 and described in Table 25 . Indicates
SYSCLK on/off status. Actual default is determined by actual clock on/off status, which depends on the
D[n]EN bit in PLLDIV[n] default.
Figure 19. SYSCLK Status Register (SYSTAT)
31 16
Reserved
R-0
15 3 2 1 0
Reserved SYS3ON SYS2ON SYS1ON
R-0 R-0 or 1 (1) R-1 (2) R-1
LEGEND: R = Read only; -n = value after reset
(1) For PLLC1, SYS3ON defaults to 1; for PLLC2, SYS3ON is reserved and defaults to 0.
(2) For PLLC1, SYS2ON defaults to 1; for PLLC2, SYS2ON is reserved and defaults to 1.
Table 25. SYSCLK Status Register (SYSTAT) Field Descriptions
Bit Field Value Description
31-3 Reserved 0 Reserved
2 SYS3ON SYSCLK3 on status. SYSCLK3 is controlled in the PLL controller divider 3 register (PLLDIV3). Not
applicable on PLLC2 (this bit is reserved).
0 SYSCLK3 is off.
1 SYSCLK3 is on.
1 SYS2ON SYSCLK2 on status. SYSCLK2 is controlled in the PLL controller divider 2 register (PLLDIV2). Not
applicable on PLLC2 (this bit is reserved).
0 SYSCLK2 is off.
1 SYSCLK2 is on.
0 SYS1ON SYSCLK1 on status. SYSCLK1 is controlled in the PLL controller divider 1 register (PLLDIV1).
0 SYSCLK1 is off.
1 SYSCLK1 is on.
SPRUES0B – December 2007 Phase-Locked Loop Controller (PLLC) 33
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