Texas Instruments TMS320C642x DSP - Manual (Page 24)

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2.4.4 PLL Multiplier Control Register (PLLM)
2.4.5 PLL Controller Divider 1 Register (PLLDIV1)
PLL Controller
The PLL multiplier control register (PLLM) is shown in Figure 7 and described in Table 13 .
Figure 7. PLL Multiplier Control Register (PLLM)
31 16
Reserved
R-0
15 5 4 0
Reserved PLLM
R-0 R/W-10h or 13h (1)
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
(1) For PLLC1, PLLM defaults to 10h (PLL multiply by 17); For PLLC2, PLLM defaults to 13h (PLL multiply by 20).
Table 13. PLL Multiplier Control Register (PLLM) Field Descriptions
Bit Field Value Description
31-5 Reserved 0 Reserved
4-0 PLLM 0-1Fh PLL multiplier select. Multiplier value = PLLM + 1. For example, PLLM = 16 (10h) means multiply by 17.
See device-specific data manual for valid multiplier values for each PLL.
The PLL controller divider 1 register (PLLDIV1) is shown in Figure 8 and described in Table 14 . Divider 1
controls divider for SYSCLK1.
Figure 8. PLL Controller Divider 1 Register (PLLDIV1)
31 16
Reserved
R-0
15 14 5 4 0
D1EN Reserved RATIO
R/W-0 R-0 R/W-0 or 1 (1)
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
(1) For PLLC1, RATIO defaults to 0 (PLL1 divide by 1); for PLLC2, RATIO defaults to 1 (PLL2 divide by 2).
Table 14. PLL Controller Divider 1 Register (PLLDIV1) Field Descriptions
Bit Field Value Description
31-16 Reserved 0 Reserved
15 D1EN Divider 1 enable.
0 Divider 1 is disabled.
1 Divider 1 is enabled.
14-5 Reserved 0 Reserved
4-0 RATIO 0-1Fh Divider ratio. Divider value = RATIO + 1. For example, RATIO = 0 means divide by 1.
24 Phase-Locked Loop Controller (PLLC) SPRUES0B – December 2007
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