1 device clock generation, 2 steps for changing pll1/core domain frequency, 1 initialization to pll mode from pll power down – Texas Instruments TMS320C642x DSP User Manual
Page 13: Clocks
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2.2.1
Device Clock Generation
2.2.2
Steps for Changing PLL1/Core Domain Frequency
2.2.2.1
Initialization to PLL Mode from PLL Power Down
PLL Controller
PLLC1 generates several clocks from the PLL1 output clock for use by the various processors and
modules. These are summarized in
. SYSCLK1, SYSCLK2, and SYSCLK3 must maintain a fixed
frequency ratio requirement, no matter what reference clock (PLL or bypass) or PLL frequency is used.
Table 6. System PLLC1 Output Clocks
PLLC1 Output Clock
Used by
Default Divider
SYSCLK1
DSP
/1
SYSCLK2
SCR, EDMA, CLKDIV3 Domain peripherals
/3
SYSCLK3
CLKDIV6 Domain peripherals
/6
AUXCLK
CLKIN Domain peripherals
NA
OBSCLK
CLKOUT0 source
/1
Refer to the appropriate subsection on how to program the PLL1/Core Domain clocks:
•
If the PLL is powered down (PLLPWRDN bit in PLLCTL is set to 1), follow the full PLL initialization
procedure in
to initialize the PLL.
•
If the PLL is not powered down (PLLPWRDN bit in PLLCTL is cleared to 0), follow the sequence in
to change the PLL multiplier.
•
If the PLL is already running at a desired multiplier and you only want to change the SYSCLK dividers,
follow the sequence in
Note that the PLL is powered down after the following device-level global resets:
•
Power-on Reset (POR)
•
Warm Reset (RESET)
•
Max Reset
If the PLL is powered down (PLLPWRDN bit in PLLCTL is set to 1), you must follow the procedure below
to change PLL1 frequencies. The recommendation is to stop all peripheral operation before changing the
PLL1 frequency, with the exception of the C64x+ DSP and DDR2. The C64x+ DSP must be operational to
program the PLL controller. DDR2 operates off of the clock from PLLC2.
1. Select the clock mode by programming the CLKMODE bit in PLLCTL.
2. Before changing the PLL frequency, switch to PLL bypass mode:
a. Clear the PLLENSRC bit in PLLCTL to 0 to allow PLLCTL.PLLEN to take effect.
b. Clear the PLLEN bit in PLLCTL to 0 (select PLL bypass mode).
c. Wait for 4 MXI cycles to ensure PLLC switches to bypass mode properly.
3. Clear the PLLRST bit in PLLCTL to 0 (reset PLL)
4. Set the PLLDIS bit in PLLCTL to 1 (disable PLL output).
5. Clear the PLLPWRDN bit in PLLCTL to 0 to bring the PLL out of power-down mode.
6. Clear the PLLDIS bit in PLLCTL to 0 (enable the PLL) to allow PLL outputs to start toggling. Note that
the PLLC is still at PLL bypass mode; therefore, the toggling PLL output does not get propagated to
the rest of the device.
7. Wait for PLL stabilization time. See the device-specific data manual for PLL stabilization time.
8. Program the required multiplier value in PLLM.
SPRUES0B – December 2007
Phase-Locked Loop Controller (PLLC)
13