2 initialization to pll mode from pll power down, Section 2.3.2.2, Example 2 – Texas Instruments TMS320C642x DSP User Manual
Page 18: Example 3
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2.3.2.2
Initialization to PLL Mode from PLL Power Down
PLL Controller
Example 2. PLL2 Frequency Change Steps When DDR2 Memory Controller is In Reset
This example discusses the steps to change the PLL2 frequency when the DDR2 memory controller is
in reset. Note that the DDR2 memory controller is in reset after these device-level global resets:
power-on reset, warm reset, max reset.
1. Leave the DDR2 memory controller in reset.
2. Program the PLL2 clocks by following the steps in the appropriate section:
, or
. (Discussion in
explains which is the appropriate
subsection).
3. Initialize the DDR2 memory controller. The steps for DDR2 memory controller initialization are found
in the TMS320C642x DSP DDR2 Memory Controller User's Guide
).
Example 3. PLL2 Frequency Change Steps When DDR2 Memory Controller is Out of Reset
This example discusses the steps to change the PLL2 frequency when the DDR2 memory controller is
already out of reset.
1. Stop DDR2 memory controller accesses and purge any outstanding requests.
2. Put the DDR2 memory in self-refresh mode and stop the DDR2 memory controller clock. The DDR2
memory controller clock shut down sequence is in the TMS320C642x DSP DDR2 Memory
Controller User's Guide (
3. Program the PLL2 clocks by following the steps in the appropriate section:
, or
. (Discussion in
explains which is the appropriate
subsection).
4. Re-enable the DDR2 memory controller clock. The DDR2 memory controller clock on sequence is in
the TMS320C642x DSP DDR2 Memory Controller User's Guide
If the PLL is powered down (PLLPWRDN bit in PLLCTL is set to 1), you must follow the procedure below
to change PLL2 frequencies.
1. Select the clock mode by programming the CLKMODE bit in PLLCTL.
2. Before changing the PLL frequency, switch to PLL bypass mode:
a. Clear the PLLENSRC bit in PLLCTL to 0 to allow PLLCTL.PLLEN to take effect.
b. Clear the PLLEN bit in PLLCTL to 0 (select PLL bypass mode).
c. Wait for 4 MXI cycles to ensure PLLC switches to bypass mode properly.
3. Clear the PLLRST bit in PLLCTL to 0 (reset PLL)
4. Set the PLLDIS bit in PLLCTL to 1 (disable PLL output).
5. Clear the PLLPWRDN bit in PLLCTL to 0 to bring the PLL out of power-down mode.
6. Clear the PLLDIS bit in PLLCTL to 0 (enable the PLL) to allow PLL outputs to start toggling. Note that
the PLLC is still at PLL bypass mode; therefore, the toggling PLL output does not get propagated to
the rest of the device.
7. Wait for PLL stabilization time. See the device-specific data manual for PLL stabilization time.
18
Phase-Locked Loop Controller (PLLC)
SPRUES0B – December 2007