Texas Instruments TMS320C642x DSP - Manual (Page 27)

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2.4.9 Bypass Divider Register (BPDIV)
PLL Controller
The bypass divider register (BPDIV) is shown in Figure 12 and described in Table 18 . Bypass divider
controls divider for SYSCLKBP, dividing down from the MXI/CLKIN clock. BPDIV is not used for PLLC1.
Figure 12. Bypass Divider Register (BPDIV)
31 16
Reserved
R-0
15 14 5 4 0
BPDEN Reserved RATIO
R/W-1 R-0 R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 18. Bypass Divider Register (BPDIV) Field Descriptions
Bit Field Value Description
31-16 Reserved 0 Reserved
15 BPDEN Bypass divider enable.
0 Bypass divider is disabled.
1 Bypass divider is enabled.
14-5 Reserved 0 Reserved
4-0 RATIO 0-1Fh Divider ratio. Divider value = RATIO + 1. For example, RATIO = 0 means divide by 1.
SPRUES0B – December 2007 Phase-Locked Loop Controller (PLLC) 27
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