Texas Instruments TMS320C642x DSP - Manual (Page 4)

List of Figures
1 Overall Clocking Diagram ................................................................................................... 7
2 PLL1 Structure in the TMS320C642x DSP ............................................................................. 12
3 PLL2 Structure in the TMS320C642x DSP
.............................................................................
16
4 Peripheral ID Register (PID) .............................................................................................. 22
5 Reset Type Status Register (RSTYPE) ................................................................................. 22
6 PLL Control Register (PLLCTL)
..........................................................................................
23
7 PLL Multiplier Control Register (PLLM) ................................................................................. 24
8 PLL Controller Divider 1 Register (PLLDIV1) ........................................................................... 24
9 PLL Controller Divider 2 Register (PLLDIV2)
..........................................................................
25
10 PLL Controller Divider 3 Register (PLLDIV3) .......................................................................... 25
11 Oscillator Divider 1 Register (OSCDIV1) ................................................................................ 26
12 Bypass Divider Register (BPDIV)
........................................................................................
27
13 PLL Controller Command Register (PLLCMD) ......................................................................... 28
14 PLL Controller Status Register (PLLSTAT) ............................................................................. 28
15 PLL Controller Clock Align Control Register (ALNCTL)
...............................................................
29
16 PLLDIV Ratio Change Status Register (DCHANGE) .................................................................. 30
17 Clock Enable Control Register (CKEN) ................................................................................. 31
18 Clock Status Register (CKSTAT)
........................................................................................
32
19 SYSCLK Status Register (SYSTAT) ..................................................................................... 33
List of Tables
1 System Clock Modes and Fixed Ratios for Core Clock Domains
.....................................................
6
2 Example PLL1 Frequencies and Dividers (25 MHZ Clock Input)
......................................................
8
3 Example PLL2 Frequencies (Core Voltage = 1.2V) ..................................................................... 9
4 Example PLL2 Frequencies (Core Voltage = 1.05V) ................................................................... 9
5 Peripheral I/O Domain Clock
.............................................................................................
10
6 System PLLC1 Output Clocks ............................................................................................ 13
7 DDR PLLC2 Output Clocks ............................................................................................... 17
8 PLL and Reset Controller List ............................................................................................ 21
9 PLL and Reset Controller Registers
.....................................................................................
21
10 Peripheral ID Register (PID) Field Descriptions ........................................................................ 22
11 Reset Type Status Register (RSTYPE) Field Descriptions ........................................................... 22
12 PLL Control Register (PLLCTL) Field Descriptions .................................................................... 23
13 PLL Multiplier Control Register (PLLM) Field Descriptions
...........................................................
24
14 PLL Controller Divider 1 Register (PLLDIV1) Field Descriptions .................................................... 24
15 PLL Controller Divider 2 Register (PLLDIV2) Field Descriptions .................................................... 25
16 PLL Controller Divider 3 Register (PLLDIV3) Field Descriptions
....................................................
25
17 Oscillator Divider 1 Register (OSCDIV1) Field Descriptions
.........................................................
26
18 Bypass Divider Register (BPDIV) Field Descriptions .................................................................. 27
19 PLL Controller Command Register (PLLCMD) Field Descriptions ................................................... 28
20 PLL Controller Status Register (PLLSTAT) Field Descriptions
.......................................................
28
21 PLL Controller Clock Align Control Register (ALNCTL) Field Descriptions
........................................
29
22 PLLDIV Ratio Change Status Register (DCHANGE) Field Descriptions ........................................... 30
23 Clock Enable Control Register (CKEN) Field Descriptions ........................................................... 31
24 Clock Status Register (CKSTAT) Field Descriptions
..................................................................
32
25 SYSCLK Status Register (SYSTAT) Field Descriptions .............................................................. 33
A-1 Document Revision History ............................................................................................... 34
4 List of Figures SPRUES0B – December 2007
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