1 device clock generation, 2 steps for changing pll1/core domain frequency, 1 initialization to pll mode from pll power down – Texas Instruments TMS320C642x DSP User Manual

1 device clock generation, 2 steps for changing pll1/core domain frequency, 1 initialization to pll mode from pll power down | Clocks | Texas Instruments TMS320C642x DSP User Manual | Page 13 / 35