SMC Networks ARM PL241 - Manual (Page 78)

Programmer’s Model
3-18 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B
3.3.11 SMC User Status Register at 0x1200
The smc_user_status Register is a general purpose read-only register that returns the
state on the smc_user_status[7:0] primary inputs. The smc_user_status Register can be
read in all states. Figure 3-16 shows the register bit assignments.
Figure 3-16 smc_user_status Register bit assignments
Table 3-12 lists the register bit assignments.
[6] wr_sync When set, the memory operates in write sync mode.
[5:3] rd_bl Determines the memory burst lengths for reads:
b000 = 1 beat
b001 = 4 beats
b010 = 8 beats
b011 = 16 beats
b100 = 32 beats
b101 = continuous
b110-b111 = reserved.
[2] rd_sync When set, the memory operates in read sync mode.
[1:0] mw Determines the SMC memory data bus width:
b00 = 8 bits
b01 = 16 bits
b10 = 32 bits
b11 = reserved.
Table 3-11 smc_opmode Register bit assignments (continued)
Bits Name Function
VPFBXVHUBVWDWXV 8QGHILQHG
Table 3-12 smc_user_status Register bit assignments
Bits Name Function
[31:8] - Reserved, read undefined
[7:0] smc_user_status The value returns the state of the smc_user_status[7:0] primary input pins