SMC Networks ARM PL241 - Manual (Page 42)

Functional Overview
2-22 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B
2.4.6 Memory manager operation
The memory manager module is responsible for controlling the state of the SMC and
the updating of chip configuration registers.
This subsection describes:
• Low-power operation
• Chip configuration registers
• Direct commands on page 2-24.
Low-power operation
The SMC accepts requests to enter the Low-power state through either the SMC
low-power interface or the APB register interface.
The SMC does not enter the power-down state until it has received an idle indication
from all areas of the peripheral, that is:
• there is no valid transfer held in the Format block
• there are no valid transfers held in the SMC interface
• all FIFOs are empty
• all memory interface blocks are IDLE.
When the Low-power state is entered, no new memory transfers are accepted until the
SMC has been moved out of Low-power state. The SMC does not request to move out
of Low-power state, and never refuses a power-down request.
Chip configuration registers
The SMC provides a mechanism for synchronizing the switching of operating modes of
the SMC with that of the memory device.
The smc_set_cycles Register and smc_set_opmode Register act as holding registers for
new operating parameters until the SMC detects the memory device has switched
modes.
Figure 2-11 on page 2-23 shows the memory manager containing a bank of registers for
each memory chip supported by the SMC. The manager register bank consists of all the
timing parameters smc_sram_cycles0_<0-3> and smc_opmode0_<0-3>, that are
required for the controller to correctly time any type of access to a supported memory
type.